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path: root/cesar/hal/phy/src/pbdma.c
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/* Cesar project {{{
 *
 * Copyright (C) 2008 Spidcom
 *
 * <<<Licence>>>
 *
 * }}} */
/**
 * \file    hal/phy/src/pbdma.c
 * \brief   HAL Phy PB DMA functions.
 * \ingroup hal_phy
 */
#include "common/std.h"

#include "inc/context.h"
#include "inc/regs.h"

#include "hal/arch/arch.h"

void ARCH_ILRAM
phy_pbdma_start (phy_t *ctx, bool bypass_aes,
                 const u32 nek[4], uint nb_total, uint nb_ready,
                 uint nb_pb_it, phy_pb_t *first_pb,
                 phy_chandata_t *first_chandata, bool now)
{
    dbg_claim (ctx);
    dbg_claim ((bypass_aes == true)
               || (bypass_aes == false && nek));
    dbg_claim (nb_total > 0 && nb_total < 255
               && nb_total >= nb_ready
               && nb_total >= nb_pb_it);
    dbg_claim_ptr (first_pb);
    dbg_claim (ARCH_DMA_VALID (first_pb));
    if (first_chandata)
    {
        dbg_claim_ptr (first_chandata);
        dbg_claim (ARCH_DMA_VALID (first_chandata));
    }
    /* Set PB parameters. */
    arch_write_buffer_flush ();
    PHY_PBDMA_PTR_PB_DESC = (u32) first_pb;
    PHY_PBDMA_PTR_CHANDATA = (u32) first_chandata;
    PHY_PBDMA_CONFIG_PB = BF_FILL (PHY_PBDMA_CONFIG_PB,
                                   (PB_NB_TOTAL, nb_total),
                                   (PB_NB_READY, nb_ready),
                                   (PB_NB_IT, nb_pb_it ? nb_pb_it : 0xff));
    /* Set encryption parameters. */
    if (!bypass_aes)
    {
        /* Hardware registers are inverted. */
        PHY_PBDMA_KEY_0 = nek[3];
        PHY_PBDMA_KEY_1 = nek[2];
        PHY_PBDMA_KEY_2 = nek[1];
        PHY_PBDMA_KEY_3 = nek[0];
    }
    /* Configure. */
    u32 conf = PHY_PBDMA_CTRL_CONFIG__DEFAULT
        | BF_MASK (PHY_PBDMA_CTRL_CONFIG__START_DATA);
    if (bypass_aes)
        conf |= BF_MASK (PHY_PBDMA_CTRL_CONFIG__AES_BYPASS);
    if (first_chandata)
        conf |= BF_MASK (PHY_PBDMA_CTRL_CONFIG__START_CHANDATA);
    PHY_PBDMA_CTRL_CONFIG = conf;
    /* Start right now (for RX). */
    if (now)
        PHY_PRATIC_IMMEDIATE_ACTION = PHY_PRATIC_ACTION__PBD_START;
    /* Trace once finished. */
    PHY_TRACE (PBDMA_START, phy_date (ctx), bypass_aes, nb_total, nb_ready,
               nb_pb_it, first_chandata ? true : false, now);
}

void ARCH_ILRAM
phy_pbdma_update (phy_t *ctx, uint nb_ready, uint nb_pb_it)
{
    dbg_claim (ctx);
    PHY_TRACE (PBDMA_UPDATE, nb_ready, nb_pb_it);
    uint nb_total = BF_GET (PHY_PBDMA_CONFIG_PB__PB_NB_TOTAL,
                            PHY_PBDMA_CONFIG_PB);
    dbg_claim (nb_total > 0 && nb_total < 255
               && nb_total >= nb_ready
               && nb_total >= nb_pb_it);
    PHY_PBDMA_CONFIG_PB = BF_FILL (PHY_PBDMA_CONFIG_PB,
                                   (PB_NB_TOTAL, nb_total),
                                   (PB_NB_READY, nb_ready),
                                   (PB_NB_IT, nb_pb_it ? nb_pb_it : 0xff));
}

phy_pb_t * ARCH_ILRAM
phy_pbdma_get_tail (phy_t *ctx)
{
    return (phy_pb_t *) PHY_PBDMA_PTR_PB_DESC;
}

volatile const u32 * ARCH_ILRAM
phy_pbdma_get_crc_bitmap (phy_t *ctx)
{
    return &PHY_PBDMA_SACKI_BITMAP_0;
}

void ARCH_ILRAM
phy_pbdma_start_chandata (phy_t *ctx, phy_chandata_t *first_chandata)
{
    dbg_claim (ctx);
    dbg_claim_ptr (first_chandata);
    dbg_claim (ARCH_DMA_VALID (first_chandata));
    PHY_TRACE (PBDMA_START_CHANDATA);
    arch_write_buffer_flush ();
    PHY_PBDMA_PTR_CHANDATA = (u32) first_chandata;
    PHY_PBDMA_CTRL_CONFIG = PHY_PBDMA_CTRL_CONFIG__DEFAULT
        | BF_MASK (PHY_PBDMA_CTRL_CONFIG__START_CHANDATA)
        | BF_MASK (PHY_PBDMA_CTRL_CONFIG__CHANDATA_WAIT_START);
}