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#ifndef hal_phy_inc_bridgedma_proto_h
#define hal_phy_inc_bridgedma_proto_h
/* Cesar project {{{
 *
 * Copyright (C) 2008 Spidcom
 *
 * <<<Licence>>>
 *
 * }}} */
/**
 * \file    hal/phy/inc/bridgedma_proto.h
 * \brief   Context for the bridge dma prototype version.
 * \ingroup hal_phy
 *
 */
#include "hal/phy/bridgedma.h"

#include <cyg/kernel/kapi.h>
#include <cyg/hal/hal_arch.h>
#include <cyg/hal/hal_intr.h>

#include "lib/crc.h"
#include "lib/utils.h"

#include "hal/phy/inc/bridgedma_it_mgr.h"

#define BRIDGEDMA_THREAD_PRIORITY 0
#define BRIDGEDMA_THREAD_STACK_SIZE CYGNUM_HAL_STACK_SIZE_TYPICAL

/* Use this define to enable or disable the it. It corresponds to the bit 13
 * in the eCos it register. */
#define BRIDGEDMA_ECOS_IT 13
#define BRIDGEDMA_ECOS_IT_MASK (1 << BRIDGEDMA_ECOS_IT)

#ifdef __sparc__

#define bridgedma_crc_compute_continue_block crc_compute_continue_block_le
#define bridgedma_crc_compute_block crc_compute_block_le

#define BRIDGEDMA_PROTO_ECOS_IT_BASE_REGISTER 0x80000098
#define BRIDGEDMA_PROTO_ECOS_IT_ENABLE_REGISTER \
    BRIDGEDMA_PROTO_ECOS_IT_BASE_REGISTER
#define BRIDGEDMA_PROTO_ECOS_IT_DISABLE_REGISTER \
    (BRIDGEDMA_PROTO_ECOS_IT_BASE_REGISTER + 4)

#else /* ! __sparc__ */

#define BRIDGEDMA_PROTO_ECOS_IT_BASE_REGISTER (& synth_pending_isrs)
#define BRIDGEDMA_PROTO_ECOS_IT_ENABLE_REGISTER \
    BRIDGEDMA_PROTO_ECOS_IT_BASE_REGISTER
#define BRIDGEDMA_PROTO_ECOS_IT_DISABLE_REGISTER \
    BRIDGEDMA_PROTO_ECOS_IT_BASE_REGISTER

#define bridgedma_crc_compute_continue_block crc_compute_continue_block
#define bridgedma_crc_compute_block crc_compute_block

#endif /* ! __sparc__ */


#define PHY_HAL_INTERRUPT_PRIORITY    1 /* is it the right value ? */

#define HPAV_CRC32_GENERATOR 0x04c11db7
#define HPAV_CRC32_INIT      0xffffffff
#define HPAV_CRC32_MAGIC     0x2144df1c

/** 1 byte is processed into 5ns, so 8 bytes per tick (40ns) */
#define BRIDGEDMA_BYTE_PER_TICK  8
/** max additionnal processing time is 10us, so 250 ticks */
#define BRIDGEDMA_ADD_MAX_TICK   250


typedef enum
{
    PB_TO_MACFRAME,
    MACFRAME_TO_PB
} bridgedma_copy_dir_t;

struct phy_bridgedma_t
{
    /** The thread handle. */
    cyg_handle_t thread_handle;
    /** The thread itself. */
    cyg_thread thread;
    /** the thread stack */
    u8 thread_stack [BRIDGEDMA_THREAD_STACK_SIZE];

    /** crc context. */
    crc_t crc_ctx;
    uint icv_substitution;
    uint icv_current;

    /** Interrupt manager. */
    cyg_interrupt interrupt;
    cyg_handle_t interrupt_handle;

    /** Bridge DMA status. */
    phy_bridgedma_status_t status;

    /** Bridge job current. */
    phy_bridgedma_job_t *job_current;
    /** Bridge job first. */
    phy_bridgedma_job_t *job_first;

    /** Interruption manager. */
    phy_bridgedma_it_mgr_t it_mgr;

    /* Real phy bridgedma context. */
    /** User data passed to any callback. */
    void *user_data;
    /** Bridge DMA interrupt callback. */
    phy_bridgedma_cb_t bridgedma_cb;
    /** DSR callback. */
    phy_deferred_cb_t deferred_cb;
    /** Bridgedma last job. */
    phy_bridgedma_job_t *job_last;
};

BEGIN_DECLS

void
phy_bridgedma_proto_process (cyg_addrword_t data);

END_DECLS

#endif /* hal_phy_inc_bridgedma_proto_h */