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#ifndef hal_arch_inc_sparc_h
#define hal_arch_inc_sparc_h
/* Cesar project {{{
 *
 * Copyright (C) 2007 Spidcom
 *
 * <<<Licence>>>
 *
 * }}} */
/**
 * \file    hal/arch/inc/sparc.h
 * \brief   Sparc specific header.
 * \ingroup hal_arch
 */

#include "hal/arch/inc/regs_addr.h"

#if defined (ECOS) && ECOS

# include "config/arch/ilram.h"

# undef ARCH_ILRAM
# define ARCH_ILRAM __attribute__ ((section (".ilram")))

# undef ARCH_ILRAM_PRIO
# define ARCH_ILRAM_PRIO(prio) PASTE (ARCH_ILRAM_PRIO_, prio)

# if CONFIG_ARCH_ILRAM_PRIO >= 3
#  define ARCH_ILRAM_PRIO_3 ARCH_ILRAM
# else
#  define ARCH_ILRAM_PRIO_3
# endif
# if CONFIG_ARCH_ILRAM_PRIO >= 2
#  define ARCH_ILRAM_PRIO_2 ARCH_ILRAM
# else
#  define ARCH_ILRAM_PRIO_2
# endif
# if CONFIG_ARCH_ILRAM_PRIO >= 1
#  define ARCH_ILRAM_PRIO_1 ARCH_ILRAM
# else
#  define ARCH_ILRAM_PRIO_1
# endif
# if CONFIG_ARCH_ILRAM_PRIO >= 0
#  define ARCH_ILRAM_PRIO_0 ARCH_ILRAM
# else
#  define ARCH_ILRAM_PRIO_0
# endif

# undef ARCH_DLRAM_DATA
# define ARCH_DLRAM_DATA __attribute__ ((section (".dlram_data")))

# undef ARCH_DLRAM_BSS
# define ARCH_DLRAM_BSS __attribute__ ((section (".dlram_bss")))

#endif

#define ARCH_SDRAM_CACHED_SHIFTED_ADDR 0x00000000
#define ARCH_SDRAM_CACHED_ADDR 0x10000000
#define ARCH_SDRAM_UNCACHED_ADDR 0x40000000

#define ARCH_ADDR_ADD(addr, add) ((typeof (*addr) *) ((u8 *) (addr) + (add)))

#undef ARCH_CPU_TO_DMA
#define ARCH_CPU_TO_DMA(addr) \
    ARCH_ADDR_ADD (addr, ARCH_MARIA_RG_LEON_ADD_START \
                   - ARCH_SDRAM_CACHED_SHIFTED_ADDR \
                   + ARCH_SDRAM_CACHED_ADDR)

#undef ARCH_CPU_TO_UNCACHEABLE
#define ARCH_CPU_TO_UNCACHEABLE(addr) \
    ARCH_ADDR_ADD (addr, ARCH_MARIA_RG_LEON_ADD_START \
                   - ARCH_SDRAM_CACHED_SHIFTED_ADDR \
                   + ARCH_SDRAM_UNCACHED_ADDR)

#undef ARCH_DMA_VALID
#define ARCH_DMA_VALID(addr) (((u32) (addr) >> 28) == 1 \
                              || ((u32) (addr) >> 28) == 4)

#undef ARCH_STACK_DECLARE
#define ARCH_STACK_DECLARE(name) \
    u32 name[8 * 1024] __attribute__ ((aligned (8)))

/** Buffer used in arch_write_buffer_flush. */
extern volatile u32 arch_write_buffer_flush_buf;

extern inline void
arch_abort (void)
{
    /* Use syscall to stop processor. */
    __asm__ __volatile__ ("set 1, %%o0\n\t"
                          "ta 0" : : : "i0");
    while (1)
        ;
}

void
arch_stack_call_func (u8 *stack_begin, u8 *stack_end, void *func, ...);

#undef arch_stack_call
#define arch_stack_call(stack, func, args...) \
    arch_stack_call_func ((u8 *) (stack), (u8 *) (stack) + sizeof (stack), \
                          func, ## args)

extern inline void
arch_write_buffer_flush (void)
{
    /** Flush the write buffer by writing one word to memory, this will force
     * the CPU to make room in its write buffer and will flush it. */
    arch_reorder_barrier ();
    arch_write_buffer_flush_buf = 0;
    arch_reorder_barrier ();
}

#define ARCH_LEON_ASI_LOAD_CACHE 0
#define ARCH_LEON_ASI_UPDATE_CACHE 4

extern inline void
arch_load_cache (u32 *addr, uint n)
{
    u32 dummy;
    while (n)
    {
        __asm__ __volatile__ ("lda [%1] %2, %0" : "=r" (dummy)
                              : "r" (addr), "i" (ARCH_LEON_ASI_LOAD_CACHE)
                              : "memory");
        addr++;
        n--;
    }
}

extern inline void
arch_update_cache (u32 *addr, uint n)
{
    u32 dummy;
    while (n)
    {
        __asm__ __volatile__ ("lda [%1] %2, %0" : "=r" (dummy)
                              : "r" (addr), "i" (ARCH_LEON_ASI_UPDATE_CACHE)
                              : "memory");
        addr++;
        n--;
    }
}

extern inline int
arch_atomic_add (volatile int *p, int d)
{
    int o, n, t;
    __asm__ ("   ld %[p], %[o]"                 "\n\t"
             "1: add %[o], %[d], %[n]"          "\n\t"
             "   mov %[n], %[t]"                "\n\t"
             "   swap %[p], %[t]"               "\n\t"
             "   subcc %[t], %[o], %[d]"        "\n\t"
             "   bne,a 1b"                      "\n\t"
             "    mov %[n], %[o]"               "\n\t"
             : [p] "=m" (*p), [d] "=r" (d), [o] "=&r" (o), [n] "=&r" (n), [t] "=&r" (t)
             : "1" (d)
            );
    return n;
}

#endif /* hal_arch_inc_sparc_h */