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path: root/polux/linux-2.6.10/drivers/net/synop3504/synop3504.c
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Diffstat (limited to 'polux/linux-2.6.10/drivers/net/synop3504/synop3504.c')
-rw-r--r--polux/linux-2.6.10/drivers/net/synop3504/synop3504.c21
1 files changed, 21 insertions, 0 deletions
diff --git a/polux/linux-2.6.10/drivers/net/synop3504/synop3504.c b/polux/linux-2.6.10/drivers/net/synop3504/synop3504.c
index 43a4e46ed7..3a0a86e08a 100644
--- a/polux/linux-2.6.10/drivers/net/synop3504/synop3504.c
+++ b/polux/linux-2.6.10/drivers/net/synop3504/synop3504.c
@@ -1850,6 +1850,27 @@ synop3504_open (struct net_device *dev)
case VITESSE_VSC8601:
printk (DRV_NAME ": PHY for %s is VITESSE VSC8601 rev %u\n", dev->name,
pr->phy_rev);
+
+#ifdef CONFIG_SYNOP3504_PHY_DINI
+ /* Add a 2ns delay for TX and RX clock. */
+
+ /* In register 23 "Extended Phy Control 1", enable "RGMII skew timing
+ * compensation". */
+ SynopsysMiiWrite (tc, 23, 0x0100, AUTOMATIC_PHY_RESOLUTION);
+
+ /* To access the extended register 28E, put 1 in register 31
+ * "Extended Page Access". */
+ SynopsysMiiWrite (tc, 31, 0x0001, AUTOMATIC_PHY_RESOLUTION);
+
+ /* In register 28E "RGMII Skew Control", set both TX and RX RGMII Skew
+ * compensation to 2ns. */
+ SynopsysMiiWrite (tc, 28, 0xF000, AUTOMATIC_PHY_RESOLUTION);
+
+ /* Switch back to main register space, by putting 0 in register 31
+ * "Extended Page Access". */
+ SynopsysMiiWrite (tc, 31, 0x0000, AUTOMATIC_PHY_RESOLUTION);
+#endif /* CONFIG_SYNOP3504_PHY_DINI */
+
break;
case ICS_1893BF: