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Diffstat (limited to 'common/tools/genNVRAM/iomux_cfg.h')
-rw-r--r--common/tools/genNVRAM/iomux_cfg.h124
1 files changed, 124 insertions, 0 deletions
diff --git a/common/tools/genNVRAM/iomux_cfg.h b/common/tools/genNVRAM/iomux_cfg.h
index f6d9d77429..2c7f2ec3b6 100644
--- a/common/tools/genNVRAM/iomux_cfg.h
+++ b/common/tools/genNVRAM/iomux_cfg.h
@@ -203,4 +203,128 @@ uint32_t iomux_config_msk501_ddr2_2[] =
(uint32_t)-1
};
+/*
+ * MCR510-DDR2 ref design with :
+ * - ETH1 RMII mode
+ * - UART1 = ARM uart1
+ * - ARM GPIO = 1,3
+ * - LEON GPIO = 0,2
+ *
+ * This is the default configuration.
+ */
+uint32_t iomux_config_mcr510_ddr2[] =
+{
+ 0x00000000, 0x0000, 0xFFFF,
+ 0x00000050, 0x1022, 0x1677,
+ 0x00000080, 0x0500, 0x0F00,
+ 0x00000084, 0x0002, 0x0002,
+ 0x0000003C, 0x0004, 0x0004,
+ 0x00000048, 0x000F, 0x000F,
+ (uint32_t)-1
+};
+
+/*
+ * MCR510-DDR2 ref design with :
+ * - ETH1 RMII mode
+ * - UART1 = ARM uart1
+ * - ARM GPIO = 1,3
+ * - LEON GPIO = 0,2
+ * - PLC 200 GPO on
+ */
+uint32_t iomux_config_mcr510_ddr2_2[] =
+{
+ 0x00000000, 0x0000, 0xFFFF,
+ 0x00000050, 0x1022, 0x1677,
+ 0x00000080, 0x0501, 0x0F0F,
+ 0x00000084, 0x0002, 0x0002,
+ 0x0000003C, 0x0004, 0x0004,
+ 0x00000048, 0x000F, 0x000F,
+ (uint32_t)-1
+};
+
+/*
+ * MCR510-DDR1 ref design with :
+ * - ETH1 RMII mode
+ * - UART1 = ARM uart1
+ * - ARM GPIO = 1,3
+ * - LEON GPIO = 0,2
+ *
+ * This is the default configuration.
+ */
+uint32_t iomux_config_mcr510_ddr1_1[] =
+{
+ 0x00000000, 0x0000, 0xFFFF,
+ 0x00000050, 0x1022, 0x1677,
+ 0x00000080, 0x0500, 0x0F00,
+ 0x00000084, 0x0002, 0x0002,
+ 0x0000003C, 0x0004, 0x0004,
+ 0x00000048, 0x000F, 0x000F,
+ (uint32_t)-1
+};
+
+/*
+ * MCR510-DDR1 ref design with :
+ * - ETH1 RMII mode
+ * - UART1 = ARM uart1
+ * - ARM GPIO = 1,3
+ * - LEON GPIO = 0,2
+ * - PLC 200 GPO on
+ *
+ */
+uint32_t iomux_config_mcr510_ddr1_2[] =
+{
+ 0x00000000, 0x0000, 0xFFFF,
+ 0x00000050, 0x1022, 0x1677,
+ 0x00000080, 0x0501, 0x0F0F,
+ 0x00000084, 0x0002, 0x0002,
+ 0x0000003C, 0x0004, 0x0004,
+ 0x00000048, 0x000F, 0x000F,
+ (uint32_t)-1
+};
+
+/*
+ * MCR500-DDR2 ref design with :
+ * - ETH1 RGMII mode
+ * - ETH2 RMII mode
+ * - Internal AFE
+ * - UART1 = ARM uart1
+ * - UART2 = ARM uart2
+ * - ARM GPIO = 1,3
+ * - LEON GPIO = 0,2
+ *
+ * This is the default configuration.
+ */
+uint32_t iomux_config_mcr500_ddr2_1[] =
+{
+ 0x00000000, 0x0000, 0xFFFF,
+ 0x00000050, 0x1025, 0x1477,
+ 0x00000080, 0x0500, 0x0F00,
+ 0x00000084, 0x0002, 0x0002,
+ 0x0000003C, 0x0004, 0x0004,
+ 0x00000048, 0x000F, 0x000F,
+ (uint32_t)-1
+};
+
+/*
+ * MCR500-DDR2 ref design with :
+ * - ETH1 RGMII mode
+ * - ETH2 RMII mode
+ * - Internal AFE
+ * - UART1 = ARM uart1
+ * - UART2 = ARM uart2
+ * - ARM GPIO = 1,3
+ * - LEON GPIO = 0,2
+ * - PLC 200 GPO on
+ *
+ */
+uint32_t iomux_config_mcr500_ddr2_2[] =
+{
+ 0x00000000, 0x0000, 0xFFFF,
+ 0x00000050, 0x1025, 0x1477,
+ 0x00000080, 0x0501, 0x0F0F,
+ 0x00000084, 0x0002, 0x0002,
+ 0x0000003C, 0x0004, 0x0004,
+ 0x00000048, 0x000F, 0x000F,
+ (uint32_t)-1
+};
#endif /* __IOMUX_CFG_H */