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diff --git a/cleopatre/linux-2.6.25.10-spc300/drivers/net/arm/synop3504_reg.h b/cleopatre/linux-2.6.25.10-spc300/drivers/net/arm/synop3504_reg.h
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+#ifndef synop3504_reg_h
+#define synop3504_reg_h
+/* Cleopatre project {{{
+ *
+ * Copyright (C) 2008 SPiDCOM Technologies
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * }}} */
+/**
+ * \file driver/net/arm/synop3504_reg.h
+ * \brief Register definition for Synopsys 3504 driver.
+ * \ingroup cleopatre_net_driver.
+ */
+
+/** GMAC registers structure */
+enum GmacRegisters
+{
+ GmacConfig = 0x00, //config
+ GmacFrameFilter = 0x04, //frame filter
+ GmacHashHigh = 0x08, //multi-cast hash table high
+ GmacHashLow = 0x0C, //multi-cast hash table low
+ GmacGmiiAddr = 0x10, //GMII address
+ GmacGmiiData = 0x14, //GMII data
+ GmacFlowControl = 0x18, //Flow control
+ GmacVlan = 0x1C, //VLAN tag
+ GmacVersion = 0x20, //Version of Gmac
+
+ GmacWakeupAddr = 0x28, //Wake-up frame filter adrress reg
+ GmacPmtCtrlStatus = 0x2C, //PMT control and status register
+
+ GmacIntStatus = 0x38, //Gmac interupt status
+ GmacIntMask = 0x3C, //Gmac interupt status
+ GmacAddr0High = 0x40, //address0 high
+ GmacAddr0Low = 0x44, //address0 low
+ GmacAddr1High = 0x48, //address1 high
+ GmacAddr1Low = 0x4C, //address1 low
+ GmacAddr2High = 0x50, //address2 high
+ GmacAddr2Low = 0x54, //address2 low
+ GmacAddr3High = 0x58, //address3 high
+ GmacAddr3Low = 0x5C, //address3 low
+ GmacAddr4High = 0x60, //address4 high
+ GmacAddr4Low = 0x64, //address4 low
+ GmacAddr5High = 0x68, //address5 high
+ GmacAddr5Low = 0x6C, //address5 low
+ GmacAddr6High = 0x70, //address6 high
+ GmacAddr6Low = 0x74, //address6 low
+ GmacAddr7High = 0x78, //address7 high
+ GmacAddr7Low = 0x7C, //address7 low
+ GmacAddr8High = 0x80, //address8 high
+ GmacAddr8Low = 0x84, //address8 low
+ GmacAddr9High = 0x88, //address9 high
+ GmacAddr9Low = 0x8C, //address9 low
+ GmacAddr10High = 0x90, //address10 high
+ GmacAddr10Low = 0x94, //address10 low
+ GmacAddr11High = 0x98, //address11 high
+ GmacAddr11Low = 0x9C, //address11 low
+ GmacAddr12High = 0xA0, //address12 high
+ GmacAddr12Low = 0xA4, //address12 low
+ GmacAddr13High = 0xA8, //address13 high
+ GmacAddr13Low = 0xAC, //address13 low
+ GmacAddr14High = 0xB0, //address14 high
+ GmacAddr14Low = 0xB4, //address14 low
+ GmacAddr15High = 0xB8, //address15 high
+ GmacAddr15Low = 0xBC, //address15 low
+ // AN registers
+ GmacANControl = 0xC0, //AN Control
+ GmacANStatus = 0xC4, //AN Status
+ GmacANAdwert = 0xC8, //AN Advertisement
+ GmacANLPA = 0xCC, //AN Link Partner Abilitye
+ GmacANExpansion = 0xD0, //AN Expansion
+ GmacTBIExStatus = 0xD4, //TBI Extended Status
+};
+
+/** DMA registers structure */
+enum DmaRegisters
+{
+ DmaBusMode = 0x00, //CSR0 - Bus Mode
+ DmaTxPollDemand = 0x04, //CSR1 - Transmit Poll Demand
+ DmaRxPollDemand = 0x08, //CSR2 - Receive Poll Demand
+ DmaRxBaseAddr = 0x0C, //CSR3 - Receive list base address
+ DmaTxBaseAddr = 0x10, //CSR4 - Transmit list base address
+ DmaStatus = 0x14, //CSR5 - Dma status
+ DmaControl = 0x18, //CSR6 - Dma control
+ DmaInterrupt = 0x1C, //CSR7 - Interrupt enable
+ DmaMissedFr = 0x20, //CSR8 - Missed Frame Counter
+
+ DmaTxCurrDesc = 0x48, //CSR20 - Current host transmit buffer address
+ DmaRxCurrDesc = 0x4C, //CSR20 - Current host receive buffer address
+ DmaTxCurrBuff = 0x50, //CSR21 - Current host transmit buffer address
+ DmaRxCurrBuff = 0x54, //CSR21 - Current host receive buffer address
+};
+
+/** GmacConfig registers field */
+enum GmacConfigReg
+{
+ GmacWatchdogDisable = 0x00800000, //Disable watchdog timer on Rx
+ GmacWatchdogEnable = 0x00000000, //Enable watchdog timer
+
+ GmacJabberDisable = 0x00400000, //Disable jabber timer on Tx
+ GmacJabberEnable = 0x00000000, //Enable jabber timer
+
+ GmacFrameBurstEnable = 0x00200000, //Enable frame bursting during Tx
+ GmacFrameBurstDisable = 0x00000000, //Disable frame bursting
+
+ GmacJumboFrameEnable = 0x00100000, //Enable jumbo frame for Tx
+ GmacJumboFrameDisable = 0x00000000, //Disable jumbo frame
+
+ GmacInterFrameGap7 = 0x000E0000, //Config7 - 40 bit times
+ GmacInterFrameGap6 = 0x000C0000, //Config6 - 48 bit times
+ GmacInterFrameGap5 = 0x000A0000, //Config5 - 56 bit times
+ GmacInterFrameGap4 = 0x00080000, //Config4 - 64 bit times
+ GmacInterFrameGap3 = 0x00040000, //Config3 - 72 bit times
+ GmacInterFrameGap2 = 0x00020000, //Config2 - 80 bit times
+ GmacInterFrameGap1 = 0x00010000, //Config1 - 88 bit times
+ GmacInterFrameGap0 = 0x00000000, //Config0 - 96 bit times
+
+ GmacDisableCrs = 0x00010000,
+ GmacMiiGmii = 0x00008000,
+ GmacSelectMii = 0x00008000, //Port Select-MII mode
+ GmacSelectGmii = 0x00000000, //GMII mode
+
+ GmacFESpeed100 = 0x00004000, //Fast Ethernet speed 100Mbps
+ GmacFESpeed10 = 0x00000000, //10Mbps
+
+ GmacDisableRxOwn = 0x00002000, //Disable receive own packets
+ GmacEnableRxOwn = 0x00000000, //Enable receive own packets
+
+ GmacLoopbackOn = 0x00001000, //Loopback mode for GMII/MII
+ GmacLoopbackOff = 0x00000000, //Normal mode
+
+ GmacFullDuplex = 0x00000800, //Full duplex mode
+ GmacHalfDuplex = 0x00000000, //Half duplex mode
+
+ GmacRxIpcOffload = 0x00000400, //IPC checksum offload
+
+ GmacRetryDisable = 0x00000200, //Disable Retry
+ GmacRetryEnable = 0x00000000, //Enable retransmission as per BL
+
+ GmacLinkUp = 0x00000100, //Link UP
+ GmacLinkDown = 0x00000100, //Link Down
+
+ GmacPadCrcStripEnable = 0x00000080, //Automatic Pad/Crc strip enable
+ GmacPadCrcStripDisable = 0x00000000, //Automatic Pad/Crc stripping disable
+
+ GmacBackoffLimit3 = 0x00000060, //Back-off limit in HD mode
+ GmacBackoffLimit2 = 0x00000040,
+ GmacBackoffLimit1 = 0x00000020,
+ GmacBackoffLimit0 = 0x00000000,
+
+ GmacDeferralCheckEnable = 0x00000010, //Deferral check enable in HD mode
+ GmacDeferralCheckDisable = 0x00000000, //Deferral check disable
+
+ GmacTxEnable = 0x00000008, //Transmitter enable
+ GmacTxDisable = 0x00000000, //Transmitter disable
+
+ GmacRxEnable = 0x00000004, //Receiver enable
+ GmacRxDisable = 0x00000000, //Receiver disable
+};
+
+/** GmacFrameFilter registers field */
+enum GmacFrameFilterReg
+{
+ GmacFilterMask = 0x80000000,
+ GmacFilterOff = 0x80000000, //Receive all incoming packets
+ GmacFilterOn = 0x00000000, //Receive filtered packets only
+
+ GmacHashPerfectFilter = 0x00000400, //Hash or Perfect Filter enable
+
+ GmacSrcAddrFilterMask = 0x00000200,
+ GmacSrcAddrFilterEnable = 0x00000200, //Source Address Filter enable
+ GmacSrcAddrFilterDisable = 0x00000000,
+
+ GmacSrcInvaAddrFilterMask= 0x00000100,
+ GmacSrcInvAddrFilterEn = 0x00000100, //Inv Src Addr Filter enable
+ GmacSrcInvAddrFilterDis = 0x00000000,
+
+ GmacPassControlMask = 0x000000C0,
+ GmacPassControl3 = 0x000000C0, //Forwards ctrl frms that pass AF
+ GmacPassControl2 = 0x00000080, //Forwards all control frames
+ GmacPassControl1 = 0x00000040, //Does not pass control frames
+ GmacPassControl0 = 0x00000000, //Does not pass control frames
+
+ GmacBroadcastMask = 0x00000020,
+ GmacBroadcastDisable = 0x00000020, //Disable Rx of broadcast frames
+ GmacBroadcastEnable = 0x00000000, //Enable broadcast frames
+
+ GmacMulticastFilterMask = 0x00000010,
+ GmacMulticastFilterOff = 0x00000010, //Pass all multicast packets
+ GmacMulticastFilterOn = 0x00000000, //Pass filtered multicast packets
+
+ GmacDestAddrFilterMask = 0x00000008,
+ GmacDestAddrFilterInv = 0x00000008, //Inverse filtering for DA
+ GmacDestAddrFilterNor = 0x00000000, //Normal filtering for DA
+
+ GmacMcastHashFilterMask = 0x00000004,
+ GmacMcastHashFilterOn = 0x00000004, //perfom multicast hash filtering
+ GmacMcastHashFilterOff = 0x00000000, //perfect filtering only
+
+ GmacUcastHashFilterMask = 0x00000002,
+ GmacUcastHashFilterOn = 0x00000002, //Unicast Hash filtering only
+ GmacUcastHashFilterOff = 0x00000000, //perfect filtering only
+
+ GmacPromiscuousModeMask = 0x00000001,
+ GmacPromiscuousModeOn = 0x00000001, //Receive all frames
+ GmacPromiscuousModeOff = 0x00000000, //Receive filtered packets only
+};
+
+/** GmacGmiiAddr registers field */
+enum GmacGmiiAddrReg
+{
+ GmiiDevMask = 0x0000F800, //GMII device address
+ GmiiDevShift = 11,
+ GmiiRegMask = 0x000007C0, //GMII register in selected Phy
+ GmiiRegShift = 6,
+
+ GmiiCsrClkMask = 0x0000001C, //CSR Clock bit Mask
+ GmiiCsrClk5 = 0x00000014, //CSR Clock Range 250-300 MHz
+ GmiiCsrClk4 = 0x00000010, // 150-250 MHz
+ GmiiCsrClk3 = 0x0000000C, // 35-60 MHz
+ GmiiCsrClk2 = 0x00000008, // 20-35 MHz
+ GmiiCsrClk1 = 0x00000004, // 100-150 MHz
+ GmiiCsrClk0 = 0x00000000, // 60-100 MHz
+
+ GmiiWrite = 0x00000002, //Write to register
+ GmiiRead = 0x00000000, //Read from register
+
+ GmiiBusy = 0x00000001, //GMII interface is busy
+};
+
+/** GmacGmiiData registers field */
+enum GmacGmiiDataReg
+{
+ GmiiDataMask = 0x0000FFFF, //GMII Data
+};
+
+/** DmaBusMode registers field */
+enum DmaBusModeReg
+{
+ DmaFixedBurstEnable = 0x00010000, //Fixed Burst SINGLE, INCR4, INCR8 or INCR16
+ DmaFixedBurstDisable = 0x00000000, // SINGLE, INCR
+
+ DmaTxPriorityRatio11 = 0x00000000, //TX:RX DMA priority ratio 1:1
+ DmaTxPriorityRatio21 = 0x00004000, //TX:RX DMA priority ratio 2:1
+ DmaTxPriorityRatio31 = 0x00008000, //TX:RX DMA priority ratio 3:1
+ DmaTxPriorityRatio41 = 0x0000C000, //TX:RX DMA priority ratio 4:1
+
+ DmaBurstLength32 = 0x00002000, //Programmable DMA burst length = 32
+ DmaBurstLength16 = 0x00001000, //DMA burst length = 16
+ DmaBurstLength8 = 0x00000800, //DMA burst length = 8
+ DmaBurstLength4 = 0x00000400, //DMA burst length = 4
+ DmaBurstLength2 = 0x00000200, //DMA burst length = 2
+ DmaBurstLength1 = 0x00000100, //DMA burst length = 1
+ DmaBurstLength0 = 0x00000000, //DMA burst length = 0
+
+ DmaDescriptorSkip16 = 0x00000040, //Descriptor skip length (no.of dwords)
+ DmaDescriptorSkip8 = 0x00000020, //between two unchained descriptors
+ DmaDescriptorSkip4 = 0x00000010,
+ DmaDescriptorSkip2 = 0x00000008,
+ DmaDescriptorSkip1 = 0x00000004,
+ DmaDescriptorSkip0 = 0x00000000,
+
+ DmaArbitRr = 0x00000000, //DMA RR arbitration
+ DmaArbitPr = 0x00000002, //Rx has priority over Tx
+
+ DmaResetOn = 0x00000001, //Software Reset DMA engine
+ DmaResetOff = 0x00000000,
+};
+
+/** DmaControl registers field */
+enum DmaControlReg
+{
+ DmaDisableDropTcpCs = 0x04000000, //Dis. drop. of tcp/ip CS error frames
+
+ DmaStoreAndForward = 0x00200000, //Store and forward
+ DmaFlushTxFifo = 0x00100000, //Tx FIFO controller is reset to default
+
+ DmaTxThreshCtrl = 0x0001C000, //Controls thre Threh of MTL tx Fifo
+ DmaTxThreshCtrl16 = 0x0001C000, //Controls thre Threh of MTL tx Fifo 16
+ DmaTxThreshCtrl24 = 0x00018000, //Controls thre Threh of MTL tx Fifo 24
+ DmaTxThreshCtrl32 = 0x00014000, //Controls thre Threh of MTL tx Fifo 32
+ DmaTxThreshCtrl40 = 0x00010000, //Controls thre Threh of MTL tx Fifo 40
+ DmaTxThreshCtrl256 = 0x0000c000, //Controls thre Threh of MTL tx Fifo 256
+ DmaTxThreshCtrl192 = 0x00008000, //Controls thre Threh of MTL tx Fifo 192
+ DmaTxThreshCtrl128 = 0x00004000, //Controls thre Threh of MTL tx Fifo 128
+ DmaTxThreshCtrl64 = 0x00000000, //Controls thre Threh of MTL tx Fifo 64
+
+ DmaTxStart = 0x00002000, //Start/Stop transmission
+
+ DmaRxFlowCtrlDeact = 0x00001800, //Rx flow control deact. threhold
+ DmaRxFlowCtrlDeact1K = 0x00000000, //Rx flow control deact. threhold (1kbytes)
+ DmaRxFlowCtrlDeact2K = 0x00000800, //Rx flow control deact. threhold (2kbytes)
+ DmaRxFlowCtrlDeact3K = 0x00001000, //Rx flow control deact. threhold (3kbytes)
+ DmaRxFlowCtrlDeact4K = 0x00001800, //Rx flow control deact. threhold (4kbytes)
+
+ DmaRxFlowCtrlAct = 0x00001800, //Rx flow control Act.
+ DmaRxFlowCtrlAct1K = 0x00000000, //Rx flow control Act.
+ DmaRxFlowCtrlAct2K = 0x00000800, //Rx flow control Act.
+ DmaRxFlowCtrlAct3K = 0x00001000, //Rx flow control Act.
+ DmaRxFlowCtrlAct4K = 0x00001800, //Rx flow control Act.
+
+ DmaEnHwFlowCtrl = 0x00010000, //Enable HW flow control
+ DmaDisHwFlowCtrl = 0x00000000, //Disable HW flow control
+
+ DmaFwdErrorFrames = 0x00000080, //Forward error frames
+ DmaFwdUnderSzFrames = 0x00000040, //Forward undersize frames
+ DmaTxSecondFrame = 0x00000004, //Operate on second frame
+ DmaRxStart = 0x00000002, //Start/Stop reception
+};
+
+/** DmaInterrupt registers field */
+enum DmaInterruptReg
+{
+ DmaIeNormal = 0x00010000, //Normal interrupt enable
+ DmaIeAbnormal = 0x00008000, //Abnormal interrupt enable
+
+ DmaIeEarlyRx = 0x00004000, //Early receive interrupt enable
+ DmaIeBusError = 0x00002000, //Fatal bus error enable
+ DmaIeEarlyTx = 0x00000400, //Early transmit interrupt enable
+ DmaIeRxWdogTO = 0x00000200, //Receive Watchdog Timeout enable
+ DmaIeRxStopped = 0x00000100, //Receive process stopped enable
+ DmaIeRxNoBuffer = 0x00000080, //Receive buffer unavailable enable
+ DmaIeRxCompleted = 0x00000040, //Completion of frame reception enable
+ DmaIeTxUnderflow = 0x00000020, //Transmit underflow enable
+
+ DmaIeRxOverflow = 0x00000010, //Receive Buffer overflow interrupt
+ DmaIeTxJabberTO = 0x00000008, //Transmit Jabber Timeout enable
+ DmaIeTxNoBuffer = 0x00000004, //Transmit buffer unavailable enable
+ DmaIeTxStopped = 0x00000002, //Transmit process stopped enable
+ DmaIeTxCompleted = 0x00000001, //Transmit completed enable
+};
+
+#endif /* synop3504_reg_h */