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-rw-r--r--cesar/ecos/packages/hal/sparc/arch/current/include/hal_intr.h44
-rw-r--r--cesar/hal/arch/inc/ecos.h50
2 files changed, 54 insertions, 40 deletions
diff --git a/cesar/ecos/packages/hal/sparc/arch/current/include/hal_intr.h b/cesar/ecos/packages/hal/sparc/arch/current/include/hal_intr.h
index 489402b176..6f1214ec7f 100644
--- a/cesar/ecos/packages/hal/sparc/arch/current/include/hal_intr.h
+++ b/cesar/ecos/packages/hal/sparc/arch/current/include/hal_intr.h
@@ -157,6 +157,44 @@ typedef cyg_uint32 CYG_INTERRUPT_STATE;
);
+#if __WINSIZE == 2 && defined (CYGHWR_HAL_SPARC_FLAT)
+
+// Use faster and smaller interrupt enable/disable code as PSR is always
+// restored after an interrupt handler execution, read/modify/write PSR
+// sequence is safe.
+// This code also has the benefit not to stop the processor if traps are
+// disabled.
+
+#define SPARC_PSR_ET_MASK 0x20
+
+externC inline unsigned long sparc_disable_interrupts(void) {
+ unsigned long flags;
+ unsigned long tmp;
+ __asm__ __volatile__ (
+ "rd %%psr, %0\n\t"
+ "andn %0, %2, %1\n\t"
+ "wr %1, 0, %%psr\n\t"
+ "nop; nop; nop"
+ : "=&r" (flags), "=r" (tmp)
+ : "i" (SPARC_PSR_ET_MASK)
+ : "memory");
+ return flags;
+}
+
+externC inline void sparc_restore_interrupts(unsigned long flags) {
+ unsigned long tmp;
+ __asm__ __volatile__ (
+ "rd %%psr, %0\n\t"
+ "and %1, %2, %1\n\t"
+ "wr %0, %1, %%psr\n\t"
+ "nop; nop; nop"
+ : "=&r" (tmp)
+ : "r" (flags), "i" (SPARC_PSR_ET_MASK)
+ : "memory");
+}
+
+#else
+
//atomical psr set (inside a syscall trap)
externC inline unsigned long sparc_disable_interrupts(void) {
unsigned long _old_;
@@ -171,6 +209,10 @@ externC inline unsigned long sparc_disable_interrupts(void) {
return _old_;
}
+#define sparc_restore_interrupts sparc_enable_interrupts
+
+#endif // __WINSIZE == 2 && defined (CYGHWR_HAL_SPARC_FLAT)
+
//atomical psr set (inside a syscall trap)
externC inline void sparc_enable_interrupts(unsigned long old) {
@@ -187,7 +229,7 @@ externC inline void sparc_enable_interrupts(unsigned long old) {
#define HAL_DISABLE_INTERRUPTS(_old_) _old_ = sparc_disable_interrupts();
#define HAL_ENABLE_INTERRUPTS() sparc_enable_interrupts(0);
-#define HAL_RESTORE_INTERRUPTS(_old_) sparc_enable_interrupts(_old_);
+#define HAL_RESTORE_INTERRUPTS(_old_) sparc_restore_interrupts(_old_);
#define HAL_QUERY_INTERRUPTS(_old_) \
asm volatile ( \
diff --git a/cesar/hal/arch/inc/ecos.h b/cesar/hal/arch/inc/ecos.h
index bfb5a1254c..01bb119621 100644
--- a/cesar/hal/arch/inc/ecos.h
+++ b/cesar/hal/arch/inc/ecos.h
@@ -21,41 +21,19 @@
extern inline uint
arch_isr_lock (void)
{
-#ifdef __sparc__
- /* On SPARC, processor stops if traps are disabled. */
- uint lock;
- HAL_QUERY_TRAPS (lock);
-#else
- uint lock = 1;
-#endif
- if (lock)
- {
- uint flags;
- HAL_DISABLE_INTERRUPTS (flags);
- HAL_REORDER_BARRIER ();
- hal_trace_isr_locked (true);
- return flags;
- }
- else
- return 0;
+ uint flags;
+ HAL_DISABLE_INTERRUPTS (flags);
+ HAL_REORDER_BARRIER ();
+ hal_trace_isr_locked (true);
+ return flags;
}
extern inline void
arch_isr_unlock (uint flags)
{
-#ifdef __sparc__
- /* On SPARC, processor stops if traps are disabled. */
- uint unlock;
- HAL_QUERY_TRAPS (unlock);
-#else
- uint unlock = 1;
-#endif
- if (unlock)
- {
- hal_trace_isr_locked (false);
- HAL_RESTORE_INTERRUPTS (flags);
- HAL_REORDER_BARRIER ();
- }
+ hal_trace_isr_locked (false);
+ HAL_RESTORE_INTERRUPTS (flags);
+ HAL_REORDER_BARRIER ();
}
extern inline void
@@ -77,16 +55,10 @@ arch_dsr_unlock (void)
extern inline void
arch_stop (void)
{
-#ifdef __sparc__
- /* On SPARC, processor stops if traps are disabled. */
- uint et;
- HAL_QUERY_TRAPS (et);
- if (et)
- cyg_drv_isr_lock ();
-#else
- cyg_drv_isr_lock ();
-#endif
+ uint flags;
+ HAL_DISABLE_INTERRUPTS (flags);
cyg_drv_dsr_lock ();
+ HAL_REORDER_BARRIER ();
}
#define arch_reorder_barrier HAL_REORDER_BARRIER