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-rw-r--r--cesar/hal/phy/maximus/src/maximus_phy_ctrl.c5
-rw-r--r--cesar/hal/phy/phy.h7
-rw-r--r--cesar/hal/phy/src/phy.c15
3 files changed, 23 insertions, 4 deletions
diff --git a/cesar/hal/phy/maximus/src/maximus_phy_ctrl.c b/cesar/hal/phy/maximus/src/maximus_phy_ctrl.c
index 9768ab85cf..b0d94cbafc 100644
--- a/cesar/hal/phy/maximus/src/maximus_phy_ctrl.c
+++ b/cesar/hal/phy/maximus/src/maximus_phy_ctrl.c
@@ -2021,6 +2021,11 @@ phy_init (void *user_data, phy_rx_fc_cb_t rx_fc_cb, phy_access_cb_t access_cb,
return &ctx;
}
+void
+phy_check_hardware (phy_t *ctx)
+{
+ dbg_assert_ptr (ctx);
+}
/**
* set errno to:
diff --git a/cesar/hal/phy/phy.h b/cesar/hal/phy/phy.h
index 7890320510..40b9593b87 100644
--- a/cesar/hal/phy/phy.h
+++ b/cesar/hal/phy/phy.h
@@ -99,6 +99,13 @@ phy_init (void *user_data, phy_rx_fc_cb_t rx_fc_cb, phy_access_cb_t access_cb,
phy_tx_false_alarm_cb_t tx_false_alarm_cb, phy_deferred_cb_t deferred_cb);
/**
+ * Check compatibility between software and hardware.
+ * \param ctx phy context
+ */
+void
+phy_check_hardware (phy_t *ctx);
+
+/**
* Set the tone mask and its related parameters, this is a kind of
* initialisation second step.
* \param ctx phy context
diff --git a/cesar/hal/phy/src/phy.c b/cesar/hal/phy/src/phy.c
index c397eacced..f308267844 100644
--- a/cesar/hal/phy/src/phy.c
+++ b/cesar/hal/phy/src/phy.c
@@ -640,10 +640,6 @@ phy_init (void *user_data, phy_rx_fc_cb_t rx_fc_cb, phy_access_cb_t access_cb,
cyg_drv_interrupt_unmask (LEON_ITC2_HIGH_PRIORITY_ITC1_IT);
/* Activate clocks and release DSP reset. */
phy_init_dsp ();
- /* Check hardware compatibility. */
- if (!CONFIG_PHY_AES_ALWAYS_BYPASSED)
- /* No AES on MSE500 revision 1. */
- dbg_assert (arch_mse500_chip () != 1);
/* Initialise hardware. */
phy_clock_set_numerator (ctx, 1000000);
PHY_PRATIC_IMMEDIATE_ACTION = PHY_PRATIC_ACTION__INIT_TX;
@@ -726,6 +722,17 @@ phy_init (void *user_data, phy_rx_fc_cb_t rx_fc_cb, phy_access_cb_t access_cb,
return ctx;
}
+void
+phy_check_hardware (phy_t *ctx)
+{
+ dbg_assert (ctx);
+
+ /* Check hardware compatibility. */
+ if (!CONFIG_PHY_AES_ALWAYS_BYPASSED)
+ /* No AES on MSE500 revision 1. */
+ dbg_assert (arch_mse500_chip () != 1);
+}
+
static void
phy_set_robo_param (phy_t *ctx, u32 *tonemask, uint carrier_nb)
{