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-rw-r--r--polux/devkit/plc-polux/pmd/plc_pmd.h7
-rw-r--r--polux/devkit/plc-polux/pmd/pmd_core.c114
-rw-r--r--polux/include/plc/plc_v2_mse500.h75
-rw-r--r--polux/linux-2.6.10/arch/arm/mach-mse500/Kconfig13
4 files changed, 194 insertions, 15 deletions
diff --git a/polux/devkit/plc-polux/pmd/plc_pmd.h b/polux/devkit/plc-polux/pmd/plc_pmd.h
index cc1a631ea7..d2eb28e89a 100644
--- a/polux/devkit/plc-polux/pmd/plc_pmd.h
+++ b/polux/devkit/plc-polux/pmd/plc_pmd.h
@@ -411,6 +411,7 @@ struct plc_v2_setup_regs {
volatile uint16_t pad_d0[8]; /* d0-de */
volatile uint16_t pad_e0[8]; /* e0-ee */
volatile uint16_t pad_f0[8]; /* f0-fe */
+#ifndef CONFIG_CHIP_FEATURE_NO_AFE_IN_PLC_REGS
volatile uint16_t sport_command; /* 100 */
volatile uint16_t panache_mode; /* 102 */
volatile uint16_t gpo; /* 104 */
@@ -424,9 +425,9 @@ struct plc_v2_setup_regs {
volatile uint16_t sport_r_data_byte_1; /* 122 */
volatile uint16_t sport_r_data_byte_2; /* 124 */
volatile uint16_t sport_r_data_byte_3; /* 126 */
+#endif /* !CONFIG_CHIP_FEATURE_NO_AFE_IN_PLC_REGS */
};
-
/* automatic gain control registers */
struct plc_agc_regs {
volatile uint16_t enable; /* 80 */
@@ -443,12 +444,13 @@ struct plc_agc_regs {
volatile uint16_t tx_enable_delay; /* 96 */
volatile uint16_t tx_coding; /* 98 */
volatile uint16_t rx_coding; /* 9a */
-#if defined(SP_LISA) || defined(CONFIG_ARCH_MSE500)
+#if defined (SP_LISA) || defined (CONFIG_ARCH_MSE500)
volatile uint16_t unlock; /* 9c LISA BB */
volatile uint16_t attn; /* 9e LISA BB */
#endif
};
+#ifndef CONFIG_CHIP_FEATURE_NO_AFE_IN_PLC_REGS
/* analog front end parameters */
struct plc_paf_regs {
volatile uint16_t sport_command; /* 1100 */
@@ -465,6 +467,7 @@ struct plc_paf_regs {
volatile uint16_t sport_r_data_byte_2; /* 1124 */
volatile uint16_t sport_r_data_byte_3; /* 1126 */
};
+#endif /* !CONFIG_CHIP_FEATURE_NO_AFE_IN_PLC_REGS */
struct pmd_modulation_thr {
uint16_t bpsk_thr;
diff --git a/polux/devkit/plc-polux/pmd/pmd_core.c b/polux/devkit/plc-polux/pmd/pmd_core.c
index 0528a66917..611e375180 100644
--- a/polux/devkit/plc-polux/pmd/pmd_core.c
+++ b/polux/devkit/plc-polux/pmd/pmd_core.c
@@ -488,9 +488,76 @@ void pmd_load_phlic ()
agc->correction_factor = 0x600; /* facteur multiplicatif de correction- JL je l'aurais bien mis à 0x200... */
agc->max_gain = 0x58; /* gain maximum */
agc->max_pwm = 0x58; /* compteur max PWM */
-#if defined(SP_LISA) || defined(CONFIG_ARCH_MSE500)
+#if defined (SP_LISA) || defined (CONFIG_ARCH_MSE500)
agc->attn = 0x100C; /* LISA BB command external attn */
-#endif
+#endif /* defined (SP_LISA) || defined (CONFIG_ARCH_MSE500) */
+
+#ifdef CONFIG_CHIP_FEATURE_SET_HLUT
+ *((volatile uint32_t *) PMD_HLUT_TABLE_0) = 0;
+ *((volatile uint32_t *) PMD_HLUT_TABLE_1) = 1;
+ *((volatile uint32_t *) PMD_HLUT_TABLE_2) = 2;
+ *((volatile uint32_t *) PMD_HLUT_TABLE_3) = 3;
+ *((volatile uint32_t *) PMD_HLUT_TABLE_4) = 4;
+ *((volatile uint32_t *) PMD_HLUT_TABLE_5) = 5;
+ *((volatile uint32_t *) PMD_HLUT_TABLE_6) = 6;
+ *((volatile uint32_t *) PMD_HLUT_TABLE_7) = 7;
+ *((volatile uint32_t *) PMD_HLUT_TABLE_8) = 8;
+ *((volatile uint32_t *) PMD_HLUT_TABLE_9) = 9;
+ *((volatile uint32_t *) PMD_HLUT_TABLE_10) = 10;
+ *((volatile uint32_t *) PMD_HLUT_TABLE_11) = 11;
+ *((volatile uint32_t *) PMD_HLUT_TABLE_12) = 12;
+ *((volatile uint32_t *) PMD_HLUT_TABLE_13) = 13;
+ *((volatile uint32_t *) PMD_HLUT_TABLE_14) = 14;
+ *((volatile uint32_t *) PMD_HLUT_TABLE_15) = 15;
+ *((volatile uint32_t *) PMD_HLUT_TABLE_16) = 16;
+ *((volatile uint32_t *) PMD_HLUT_TABLE_17) = 17;
+ *((volatile uint32_t *) PMD_HLUT_TABLE_18) = 18;
+ *((volatile uint32_t *) PMD_HLUT_TABLE_19) = 19;
+ *((volatile uint32_t *) PMD_HLUT_TABLE_20) = 20;
+ *((volatile uint32_t *) PMD_HLUT_TABLE_21) = 21;
+ *((volatile uint32_t *) PMD_HLUT_TABLE_22) = 22;
+ *((volatile uint32_t *) PMD_HLUT_TABLE_23) = 23;
+ *((volatile uint32_t *) PMD_HLUT_TABLE_24) = 24;
+ *((volatile uint32_t *) PMD_HLUT_TABLE_25) = 25;
+ *((volatile uint32_t *) PMD_HLUT_TABLE_26) = 26;
+ *((volatile uint32_t *) PMD_HLUT_TABLE_27) = 27;
+ *((volatile uint32_t *) PMD_HLUT_TABLE_28) = 28;
+ *((volatile uint32_t *) PMD_HLUT_TABLE_29) = 29;
+ *((volatile uint32_t *) PMD_HLUT_TABLE_30) = 30;
+ *((volatile uint32_t *) PMD_HLUT_TABLE_31) = 31;
+ *((volatile uint32_t *) PMD_HLUT_TABLE_32) = 32;
+ *((volatile uint32_t *) PMD_HLUT_TABLE_33) = 33;
+ *((volatile uint32_t *) PMD_HLUT_TABLE_34) = 34;
+ *((volatile uint32_t *) PMD_HLUT_TABLE_35) = 35;
+ *((volatile uint32_t *) PMD_HLUT_TABLE_36) = 36;
+ *((volatile uint32_t *) PMD_HLUT_TABLE_37) = 37;
+ *((volatile uint32_t *) PMD_HLUT_TABLE_38) = 38;
+ *((volatile uint32_t *) PMD_HLUT_TABLE_39) = 39;
+ *((volatile uint32_t *) PMD_HLUT_TABLE_40) = 40;
+ *((volatile uint32_t *) PMD_HLUT_TABLE_41) = 41;
+ *((volatile uint32_t *) PMD_HLUT_TABLE_42) = 42;
+ *((volatile uint32_t *) PMD_HLUT_TABLE_43) = 43;
+ *((volatile uint32_t *) PMD_HLUT_TABLE_44) = 44;
+ *((volatile uint32_t *) PMD_HLUT_TABLE_45) = 45;
+ *((volatile uint32_t *) PMD_HLUT_TABLE_46) = 46;
+ *((volatile uint32_t *) PMD_HLUT_TABLE_47) = 47;
+ *((volatile uint32_t *) PMD_HLUT_TABLE_48) = 48;
+ *((volatile uint32_t *) PMD_HLUT_TABLE_49) = 49;
+ *((volatile uint32_t *) PMD_HLUT_TABLE_50) = 50;
+ *((volatile uint32_t *) PMD_HLUT_TABLE_51) = 51;
+ *((volatile uint32_t *) PMD_HLUT_TABLE_52) = 52;
+ *((volatile uint32_t *) PMD_HLUT_TABLE_53) = 53;
+ *((volatile uint32_t *) PMD_HLUT_TABLE_54) = 54;
+ *((volatile uint32_t *) PMD_HLUT_TABLE_55) = 55;
+ *((volatile uint32_t *) PMD_HLUT_TABLE_56) = 56;
+ *((volatile uint32_t *) PMD_HLUT_TABLE_57) = 57;
+ *((volatile uint32_t *) PMD_HLUT_TABLE_58) = 58;
+ *((volatile uint32_t *) PMD_HLUT_TABLE_59) = 59;
+ *((volatile uint32_t *) PMD_HLUT_TABLE_60) = 60;
+ *((volatile uint32_t *) PMD_HLUT_TABLE_61) = 61;
+ *((volatile uint32_t *) PMD_HLUT_TABLE_62) = 62;
+ *((volatile uint32_t *) PMD_HLUT_TABLE_63) = 63;
+#endif /* CONFIG_CHIP_FEATURE_SET_HLUT */
}
static void __init_afe (void)
@@ -498,15 +565,18 @@ static void __init_afe (void)
#if !defined(SP_LISA) && !defined(CONFIG_ARCH_MSE500)
struct plc_drv_unit *unit = plc_drv_get_unit (0);
#endif
- struct plc_paf_regs *paf = (struct plc_paf_regs *) PMD_PAF_REGBASE;
+
struct plc_agc_regs *agc = (struct plc_agc_regs *) PMD_AGC_REGBASE;
+#ifndef CONFIG_CHIP_MSE500DINI
+ struct plc_paf_regs *paf = (struct plc_paf_regs *) PMD_PAF_REGBASE;
+
/* PAF */
active_wait (paf_space);
paf->panache_mode = 0; /* HALF DUPLEX */
active_wait (paf_space);
-#if defined(SP_LISA) || defined(CONFIG_ARCH_MSE500)
+#if defined(SP_LISA)
// No software pin to reset the AD9865 on LISA reference design.
// The reset signal is builded by the hardware now.
paf->gpo = 0;
@@ -519,13 +589,26 @@ static void __init_afe (void)
{
paf->gpo = 72; /* reset ADC */
}
-#endif
+#endif /* SP_LISA */
+
+#else /* CONFIG_CHIP_MSE500DINI */
+ /* ADC reset. */
+ *((uint32_t *) PMD_SPARE_REG_1) |= 0x10;
+ active_wait (2000);
+#endif /* !CONFIG_CHIP_MSE500DINI */
+
active_wait (paf_space);
+#ifndef CONFIG_CHIP_FEATURE_TWOS_COMPLEMENT_AGC_CODING
agc->rx_coding = 0; /* unsigned */
+#else
+ agc->tx_coding = 1;
+ agc->rx_coding = 1;
+#endif /* !CONFIG_CHIP_FEATURE_TWOS_COMPLEMENT_AGC_CODING */
active_wait (paf_space);
agc->max_gain = 0x3f;
active_wait (paf_space);
+#ifndef CONFIG_CHIP_MSE500DINI
//****************************
// AD986X Datasheet Rev .0
// SPI Interface
@@ -537,7 +620,7 @@ static void __init_afe (void)
// ###### Half-Duplex Power Control ########
// Command x03
// 0xFF is the default value.
-#if defined(SP_LISA) || defined(CONFIG_ARCH_MSE500)
+#if defined(SP_LISA)
// Disable the control power on RX and TX Path
paf->sport_w_data_byte_3 = 0xFF & (~AD9865_ADR03__TxPWRDN) & (~AD9865_ADR03__RxPWRDN);
#else
@@ -549,7 +632,7 @@ static void __init_afe (void)
// ###### PLL Clock Multiplier / Synthesizer Control ########
// Command : 0x04 , 0x05 and 0x06
-#if defined(SP_LISA) || defined(CONFIG_ARCH_MSE500)
+#if defined(SP_LISA)
// On spc200-e, the default value is good (0x01)
// On spc200-c, the default value is never good (0x02)
// So on spc200-c, put 0x16 for a clock at 32 Mhz, and 0x01 for a clock at 64 Mhz
@@ -578,7 +661,7 @@ static void __init_afe (void)
paf->sport_command = (PAF_WRITE_COMMAND + 0x08);
-#if defined(SP_LISA) || defined(CONFIG_ARCH_MSE500)
+#if defined(SP_LISA)
// ###### Tx And Rx PGA Control ########
// Command 0x0B
paf->sport_w_data_byte_3 = 0x20;
@@ -594,7 +677,7 @@ static void __init_afe (void)
// ###### Rx Interface And Analog/Digital Loopback ########
// Command 0x0D
-#if defined(SP_LISA) || defined(CONFIG_ARCH_MSE500)
+#if defined(SP_LISA)
// Gloria Reference design appplied
paf->sport_w_data_byte_3 = 0x10;
#else
@@ -604,7 +687,7 @@ static void __init_afe (void)
active_wait (paf_space);
paf->sport_command = (PAF_WRITE_COMMAND + 0x0D);
-#if defined(SP_LISA) || defined(CONFIG_ARCH_MSE500)
+#if defined(SP_LISA)
// ###### Digital Output Drive Strength, TxDAC Output, And Rev ID ########
// Command 0x0E and 0x0F
paf->sport_w_data_byte_3 = 0x80; // Low Drive Strength activated
@@ -612,10 +695,18 @@ static void __init_afe (void)
paf->sport_command = (PAF_WRITE_COMMAND + 0x0E);
#endif
}
+#else /* CONFIG_CHIP_MSE500DINI */
+ /* Select low band. */
+ *((uint32_t *) PMD_SPARE_REG_2) = 0x000100A0;
+ active_wait (1);
+ /* DSP controlled gain mode. */
+ *((uint32_t *) PMD_SPARE_REG_2) = 0x00040000;
+#endif /* !CONFIG_CHIP_MSE500DINI */
}
void init_tx_gain(int tx_gain)
{
+#ifndef CONFIG_CHIP_MSE500DINI
/* For tx_gain, manage Register 0x0A*/
/* See AD9865 specification, p27 for correct configuration*/
struct plc_paf_regs *paf = (struct plc_paf_regs *) PMD_PAF_REGBASE;
@@ -625,7 +716,8 @@ void init_tx_gain(int tx_gain)
/* No matter of bit 7 (the 8th) */
paf->sport_w_data_byte_3 = 0x40 | tx_gain;
active_wait (paf_space);
- paf->sport_command = (PAF_WRITE_COMMAND + 0x0A);
+ paf->sport_command = (PAF_WRITE_COMMAND + 0x0A);
+#endif /* !CONFIG_CHIP_MSE500DINI */
}
diff --git a/polux/include/plc/plc_v2_mse500.h b/polux/include/plc/plc_v2_mse500.h
index e9f6bdf6ba..782a386d8b 100644
--- a/polux/include/plc/plc_v2_mse500.h
+++ b/polux/include/plc/plc_v2_mse500.h
@@ -6,7 +6,80 @@
#define PMD_SAFE_REGBASE (PMD_V2_REGBASE)
#define PMD_DSP_REGBASE (PMD_V2_REGBASE)
#define PMD_AGC_REGBASE (PMD_V2_REGBASE+0x001080)
-#define PMD_PAF_REGBASE (PMD_V2_REGBASE+0x001100)
+
+/* DINI prototype uses spare registers 1 et 2 as an equivalent
+ * to PAF registers. */
+//#define PMD_PAF_REGBASE (PMD_V2_REGBASE+0x001100)
+#define PMD_SPARE_REG_1 (0xC8040904)
+#define PMD_SPARE_REG_2 (0xC8040908)
+
+/* HLUT registers. */
+#define PMD_HLUT_BASE (PLC_BASE+0x0A000000)
+#define PMD_HLUT_TABLE_0 (PMD_HLUT_BASE + 0x000C)
+#define PMD_HLUT_TABLE_1 (PMD_HLUT_BASE + 0x0010)
+#define PMD_HLUT_TABLE_2 (PMD_HLUT_BASE + 0x0014)
+#define PMD_HLUT_TABLE_3 (PMD_HLUT_BASE + 0x0018)
+#define PMD_HLUT_TABLE_4 (PMD_HLUT_BASE + 0x001C)
+#define PMD_HLUT_TABLE_5 (PMD_HLUT_BASE + 0x0020)
+#define PMD_HLUT_TABLE_6 (PMD_HLUT_BASE + 0x0024)
+#define PMD_HLUT_TABLE_7 (PMD_HLUT_BASE + 0x0028)
+#define PMD_HLUT_TABLE_8 (PMD_HLUT_BASE + 0x002C)
+#define PMD_HLUT_TABLE_9 (PMD_HLUT_BASE + 0x0030)
+#define PMD_HLUT_TABLE_10 (PMD_HLUT_BASE + 0x0034)
+#define PMD_HLUT_TABLE_11 (PMD_HLUT_BASE + 0x0038)
+#define PMD_HLUT_TABLE_12 (PMD_HLUT_BASE + 0x003C)
+#define PMD_HLUT_TABLE_13 (PMD_HLUT_BASE + 0x0040)
+#define PMD_HLUT_TABLE_14 (PMD_HLUT_BASE + 0x0044)
+#define PMD_HLUT_TABLE_15 (PMD_HLUT_BASE + 0x0048)
+#define PMD_HLUT_TABLE_16 (PMD_HLUT_BASE + 0x004C)
+#define PMD_HLUT_TABLE_17 (PMD_HLUT_BASE + 0x0050)
+#define PMD_HLUT_TABLE_18 (PMD_HLUT_BASE + 0x0054)
+#define PMD_HLUT_TABLE_19 (PMD_HLUT_BASE + 0x0058)
+#define PMD_HLUT_TABLE_20 (PMD_HLUT_BASE + 0x005C)
+#define PMD_HLUT_TABLE_21 (PMD_HLUT_BASE + 0x0060)
+#define PMD_HLUT_TABLE_22 (PMD_HLUT_BASE + 0x0064)
+#define PMD_HLUT_TABLE_23 (PMD_HLUT_BASE + 0x0068)
+#define PMD_HLUT_TABLE_24 (PMD_HLUT_BASE + 0x006C)
+#define PMD_HLUT_TABLE_25 (PMD_HLUT_BASE + 0x0070)
+#define PMD_HLUT_TABLE_26 (PMD_HLUT_BASE + 0x0074)
+#define PMD_HLUT_TABLE_27 (PMD_HLUT_BASE + 0x0078)
+#define PMD_HLUT_TABLE_28 (PMD_HLUT_BASE + 0x007C)
+#define PMD_HLUT_TABLE_29 (PMD_HLUT_BASE + 0x0080)
+#define PMD_HLUT_TABLE_30 (PMD_HLUT_BASE + 0x0084)
+#define PMD_HLUT_TABLE_31 (PMD_HLUT_BASE + 0x0088)
+#define PMD_HLUT_TABLE_32 (PMD_HLUT_BASE + 0x008C)
+#define PMD_HLUT_TABLE_33 (PMD_HLUT_BASE + 0x0090)
+#define PMD_HLUT_TABLE_34 (PMD_HLUT_BASE + 0x0094)
+#define PMD_HLUT_TABLE_35 (PMD_HLUT_BASE + 0x0098)
+#define PMD_HLUT_TABLE_36 (PMD_HLUT_BASE + 0x009C)
+#define PMD_HLUT_TABLE_37 (PMD_HLUT_BASE + 0x00A0)
+#define PMD_HLUT_TABLE_38 (PMD_HLUT_BASE + 0x00A4)
+#define PMD_HLUT_TABLE_39 (PMD_HLUT_BASE + 0x00A8)
+#define PMD_HLUT_TABLE_40 (PMD_HLUT_BASE + 0x00AC)
+#define PMD_HLUT_TABLE_41 (PMD_HLUT_BASE + 0x00B0)
+#define PMD_HLUT_TABLE_42 (PMD_HLUT_BASE + 0x00B4)
+#define PMD_HLUT_TABLE_43 (PMD_HLUT_BASE + 0x00B8)
+#define PMD_HLUT_TABLE_44 (PMD_HLUT_BASE + 0x00BC)
+#define PMD_HLUT_TABLE_45 (PMD_HLUT_BASE + 0x00C0)
+#define PMD_HLUT_TABLE_46 (PMD_HLUT_BASE + 0x00C4)
+#define PMD_HLUT_TABLE_47 (PMD_HLUT_BASE + 0x00C8)
+#define PMD_HLUT_TABLE_48 (PMD_HLUT_BASE + 0x00CC)
+#define PMD_HLUT_TABLE_49 (PMD_HLUT_BASE + 0x00D0)
+#define PMD_HLUT_TABLE_50 (PMD_HLUT_BASE + 0x00D4)
+#define PMD_HLUT_TABLE_51 (PMD_HLUT_BASE + 0x00D8)
+#define PMD_HLUT_TABLE_52 (PMD_HLUT_BASE + 0x00DC)
+#define PMD_HLUT_TABLE_53 (PMD_HLUT_BASE + 0x00E0)
+#define PMD_HLUT_TABLE_54 (PMD_HLUT_BASE + 0x00E4)
+#define PMD_HLUT_TABLE_55 (PMD_HLUT_BASE + 0x00E8)
+#define PMD_HLUT_TABLE_56 (PMD_HLUT_BASE + 0x00EC)
+#define PMD_HLUT_TABLE_57 (PMD_HLUT_BASE + 0x00F0)
+#define PMD_HLUT_TABLE_58 (PMD_HLUT_BASE + 0x00F4)
+#define PMD_HLUT_TABLE_59 (PMD_HLUT_BASE + 0x00F8)
+#define PMD_HLUT_TABLE_60 (PMD_HLUT_BASE + 0x00FC)
+#define PMD_HLUT_TABLE_61 (PMD_HLUT_BASE + 0x0100)
+#define PMD_HLUT_TABLE_62 (PMD_HLUT_BASE + 0x0104)
+#define PMD_HLUT_TABLE_63 (PMD_HLUT_BASE + 0x0108)
+
#define PMD_DESYR_REGBASE (PMD_V2_REGBASE+0x020000)
#define PMD_FEC_DBG_ENB (PMD_FEC_REGBASE+0x0200)
diff --git a/polux/linux-2.6.10/arch/arm/mach-mse500/Kconfig b/polux/linux-2.6.10/arch/arm/mach-mse500/Kconfig
index 159b843406..4a4c4d15b1 100644
--- a/polux/linux-2.6.10/arch/arm/mach-mse500/Kconfig
+++ b/polux/linux-2.6.10/arch/arm/mach-mse500/Kconfig
@@ -12,7 +12,9 @@ config MACH_MSE500DINI
config CHIP_MSE500DINI
def_bool n
select CHIP_FEATURE_SYNOP3504_PHY_DINI
-
+ select CHIP_FEATURE_NO_AFE_IN_PLC_REGS
+ select CHIP_FEATURE_TWOS_COMPLEMENT_AGC_CODING
+ select CHIP_FEATURE_SET_HLUT
# Chip features (CHIP_FEATURE_*)
# ==============================
@@ -24,4 +26,13 @@ config CHIP_FEATURE_SYNOP3504_PHY_DINI
def_bool n
select SYNOP3504_PHY_DINI
+config CHIP_FEATURE_NO_AFE_IN_PLC_REGS
+ def_bool n
+
+config CHIP_FEATURE_TWOS_COMPLEMENT_AGC_CODING
+ def_bool n
+
+config CHIP_FEATURE_SET_HLUT
+ def_bool n
+
endmenu