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authorThierry Carré2013-02-06 15:26:53 +0100
committerThierry Carré2013-02-11 13:57:10 +0100
commit6add6686e38aad09b5f402ab3d637c2d5e5edf9f (patch)
treec54a565076962ed954c7976d11345fb9d4f4da7d /polux
parent08c5313adf7e9e2c9c4d134ccf1024e8e5dee3e0 (diff)
polux/linux/arch/arm/mse500: configure flash partitions with nvram, closes #3733
Diffstat (limited to 'polux')
-rw-r--r--polux/linux-2.6.10/arch/arm/mach-mse500/core.c4
-rw-r--r--polux/linux-2.6.10/arch/arm/mach-mse500/spi_devices.c120
2 files changed, 64 insertions, 60 deletions
diff --git a/polux/linux-2.6.10/arch/arm/mach-mse500/core.c b/polux/linux-2.6.10/arch/arm/mach-mse500/core.c
index f08fccee92..fad45a65cf 100644
--- a/polux/linux-2.6.10/arch/arm/mach-mse500/core.c
+++ b/polux/linux-2.6.10/arch/arm/mach-mse500/core.c
@@ -66,7 +66,7 @@ int mse500_autoswitch_en = 0;
void mse500_register_uart(int idx, int port);
-extern void mse500_register_spi_devices(void);
+void mse500_register_spi_devices (unsigned int nvram_offset);
#ifdef CONFIG_MMU
static struct map_desc mse500_periph_internal_desc[] __initdata = {
@@ -398,7 +398,7 @@ static void __init mse500_init(void)
#endif
mse500_init_gpio();
mse500_init_nvram (nvram_offset);
- mse500_register_spi_devices();
+ mse500_register_spi_devices (nvram_offset);
mse500_spidimg_proc_init();
#if 0
#if defined(CONFIG_CPU_MXU_ENABLE) && defined(CONFIG_CPU_RO_SRAM)
diff --git a/polux/linux-2.6.10/arch/arm/mach-mse500/spi_devices.c b/polux/linux-2.6.10/arch/arm/mach-mse500/spi_devices.c
index af44923d2d..f10cab9eab 100644
--- a/polux/linux-2.6.10/arch/arm/mach-mse500/spi_devices.c
+++ b/polux/linux-2.6.10/arch/arm/mach-mse500/spi_devices.c
@@ -27,6 +27,7 @@
#include <linux/mtd/partitions.h>
#include <asm/arch/hardware.h>
+#include <asm/arch/nvram.h>
#ifdef CONFIG_MACH_MSE500DINI_200
#define MSE500_SPI_FLASH_MAX_SPEED_HZ 10000000
@@ -34,71 +35,50 @@
#define MSE500_SPI_FLASH_MAX_SPEED_HZ 20000000
#endif
+extern spidcom_nvram_t spidcom_nvram;
+
+enum {
+ UBOOT_PART = 0,
+ NVRAM_PART,
+ USRFS_PART,
+ IMG_0_PART,
+ IMG_1_PART,
+ MAX_NB_PART
+};
+
/**
* FLASH Device Structures
+ *
+ * Note: size fields are set by 'mse500_register_spi_devices' function
+ * with nvram informations.
*/
-static struct mtd_partition mse500_flash_partitions[] = {
-#ifdef CONFIG_SLAVE
- {
- .name = "u-boot",
- .size = 0x00020000,
- .offset = 0,
- .mask_flags = 0,
- }, {
- .name = "nvram",
- .size = 0x00010000,
- .offset = MTDPART_OFS_APPEND,
- .mask_flags = 0,
- }, {
- .name = "user-fs",
- .size = 0x00080000,
- .offset = MTDPART_OFS_APPEND,
- .mask_flags = 0,
- }, {
- .name = "image 0",
- .size = 0x001b0000,
- .offset = MTDPART_OFS_APPEND,
- .mask_flags = 0,
- }, {
- .name = "image 1",
- .size = MTDPART_SIZ_FULL,
- .offset = MTDPART_OFS_APPEND,
- .mask_flags = 0,
- }
-#else
- {
- .name = "u-boot",
- .size = 0x00030000,
- .offset = 0,
- .mask_flags = 0,
- }, {
- .name = "nvram",
- .size = 0x00010000,
- .offset = MTDPART_OFS_APPEND,
- .mask_flags = 0,
- }, {
- .name = "user-fs",
- .size = 0x00100000,
- .offset = MTDPART_OFS_APPEND,
- .mask_flags = 0,
- }, {
- .name = "image 0",
- .size = 0x00360000,
- .offset = MTDPART_OFS_APPEND,
- .mask_flags = 0,
- }, {
- .name = "image 1",
- .size = MTDPART_SIZ_FULL,
- .offset = MTDPART_OFS_APPEND,
- .mask_flags = 0,
- }
-#endif /* CONFIG_SLAVE */
+static struct mtd_partition mse500_flash_partitions[MAX_NB_PART] = {
+ [UBOOT_PART] = {
+ .name = "u-boot",
+ .offset = 0,
+ .mask_flags = 0,
+ }, [NVRAM_PART] = {
+ .name = "nvram",
+ .offset = MTDPART_OFS_APPEND,
+ .mask_flags = 0,
+ }, [USRFS_PART] = {
+ .name = "user-fs",
+ .offset = MTDPART_OFS_APPEND,
+ .mask_flags = 0,
+ }, [IMG_0_PART] = {
+ .name = "image 0",
+ .offset = MTDPART_OFS_APPEND,
+ .mask_flags = 0,
+ }, [IMG_1_PART] = {
+ .name = "image 1",
+ .offset = MTDPART_OFS_APPEND,
+ .mask_flags = 0,
+ }
};
static struct flash_platform_data mse500_spiflash_data = {
.name = "spi_flash",
.parts = mse500_flash_partitions,
- .nr_parts = ARRAY_SIZE(mse500_flash_partitions),
.type = NULL,
};
@@ -135,8 +115,32 @@ static struct platform_device mse500_spictrl_device = {
.resource = mse500_spictrl_resource
};
-void __init mse500_register_spi_devices(void)
+void
+__init mse500_register_spi_devices (
+ unsigned int nvram_offset)
{
+ /* Set size of each partitions,
+ * with information found in nvram. */
+ const uint uboot_size = nvram_offset;
+ const uint nvram_size = 0x10000;
+ struct mtd_partition *mtd = mse500_flash_partitions;
+ spidcom_nvram_t *nvram = &spidcom_nvram;
+
+ mtd[UBOOT_PART].size = uboot_size;
+ mtd[NVRAM_PART].size = nvram_size;
+ mtd[USRFS_PART].size = nvram->img_0_offset - uboot_size - nvram_size;
+ mtd[IMG_0_PART].size = nvram->img_max_size;
+ mtd[IMG_1_PART].size = nvram->img_max_size;
+
+ if (2 >= nvram->nb_images)
+ mse500_spiflash_data.nr_parts = 3 + nvram->nb_images;
+ else
+ {
+ /* Image 0 and 1 partitions are valid.
+ * More image is not supported. */
+ mse500_spiflash_data.nr_parts = MAX_NB_PART;
+ }
+
platform_device_register(&mse500_spictrl_device);
spi_register_board_info(&mse500_spi_devices[0], 1);
}