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authorOlivier Dufour2012-09-17 14:11:53 +0200
committerJérémy Dufour2012-10-18 10:25:02 +0200
commite0f4e08c89c4e4e1825ff214e1245e6391b70ef7 (patch)
treed3ef3597fda4c4b27c09a2201763060132a325f2 /polux/linux-2.6.10/arch/arm
parent170f0719464382c7a45dbae9d6459daa7cbc6e1c (diff)
{cleo,polux}/linux/arm/wdt: support physical address in wdt, refs #3272
Before booting the kernel, there is not support for MMU and virtual address. This commit enables to setup and use the watchdog using physical address.
Diffstat (limited to 'polux/linux-2.6.10/arch/arm')
-rw-r--r--polux/linux-2.6.10/arch/arm/mach-mse500/wdt.c58
1 files changed, 52 insertions, 6 deletions
diff --git a/polux/linux-2.6.10/arch/arm/mach-mse500/wdt.c b/polux/linux-2.6.10/arch/arm/mach-mse500/wdt.c
index d8d70d2841..2e195b5852 100644
--- a/polux/linux-2.6.10/arch/arm/mach-mse500/wdt.c
+++ b/polux/linux-2.6.10/arch/arm/mach-mse500/wdt.c
@@ -29,9 +29,33 @@
uint32_t spc300_wdt_user_mode = 0;
EXPORT_SYMBOL(spc300_wdt_user_mode);
-int spc300_wdt_start(uint timeout_s)
+/**
+ * Refresh watchdog timer.
+ *
+ * \param va true if need to use virtual address to access register, false
+ * for physical address.
+ */
+static void spc300_wdt_refresh_(bool va)
+{
+ uint32_t reg = WDT_BF(CR, WDT_CR_VAL);
+ if (va)
+ WDT_CRR_VA = reg;
+ else
+ WDT_CRR_PA = reg;
+}
+
+/**
+ * Start watchdog timer countdown.
+ *
+ * \param timeout_s timeout of the watchdog (in second).
+ * \param va true if need to use virtual address to access register, false
+ * for physical address.
+ * \return 0 if no error, error value otherwise (-EINVAL if timeout_s is too
+ * big).
+ */
+static int spc300_wdt_start_(uint timeout_s, bool va)
{
- uint32_t cnt_value, top;
+ uint32_t cnt_value, top, reg;
//Timeout period = (2^(16+ TOP_reg)) / PCLK
@@ -47,17 +71,34 @@ int spc300_wdt_start(uint timeout_s)
{
if(cnt_value >= (1<<(top+16)))
{
- WDT_TORR_VA = WDT_BFINS(TOP, top, WDT_TORR_VA);
+ if (va)
+ WDT_TORR_VA = WDT_BFINS(TOP, top, WDT_TORR_VA);
+ else
+ WDT_TORR_PA = WDT_BFINS(TOP, top, WDT_TORR_PA);
break;
}
}
}
//Enable WDT with reset pulse = 32pclk and without interrupt management
- WDT_CR_VA = WDT_BF(RPL, 4) | WDT_BF(RMOD, 0) | WDT_BF(EN, 1);
- spc300_wdt_refresh();
+ reg = WDT_BF(RPL, 4) | WDT_BF(RMOD, 0) | WDT_BF(EN, 1);
+ if (va)
+ WDT_CR_VA = reg;
+ else
+ WDT_CR_PA = reg;
+ spc300_wdt_refresh_(va);
return 0;
}
+int spc300_wdt_start(uint timeout_s)
+{
+ return spc300_wdt_start_(timeout_s, true);
+}
+
+int spc300_wdt_start_pa(uint timeout_s)
+{
+ return spc300_wdt_start_(timeout_s, false);
+}
+
void spc300_wdt_switch(int use_umode)
{
if(use_umode)
@@ -68,7 +109,12 @@ void spc300_wdt_switch(int use_umode)
void spc300_wdt_refresh(void)
{
- WDT_CRR_VA = WDT_BF(CR, WDT_CR_VAL);
+ spc300_wdt_refresh_ (true);
+}
+
+void spc300_wdt_refresh_pa(void)
+{
+ spc300_wdt_refresh_ (false);
}
EXPORT_SYMBOL(spc300_wdt_refresh);