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authorYacine Belkadi2012-02-07 10:29:12 +0100
committerYacine Belkadi2012-06-11 13:39:26 +0200
commit222950656ee9c3e76efb33ef7382841bbd19dc07 (patch)
treebf708d22da82630cf50483837026e9ac0c379018 /polux/linux-2.6.10/arch/arm
parent3083f340c70242149e6c9823ecf7c94b269a6c19 (diff)
polux: add "mse500" target: 1) create mse500 files, refs #2944
The mse500 files are created by copying spc200c files. Copies from master at 31afe8813e218ba2bee76b3f1e653266e7f6f670 cp include/platform_lisa.h include/platform_mse500.h cp include/plc/plc_v1_lisa.h include/plc/plc_v1_mse500.h cp include/plc/plc_v2_lisa.h include/plc/plc_v2_mse500.h cp -r -v include/lisa include/mse500 cp linux-2.6.10/arch/arm/boot/compressed/head-spc2XXc.S \ linux-2.6.10/arch/arm/boot/compressed/head-mse500.S cp linux-2.6.10/arch/arm/configs/spc200c_defconfig \ linux-2.6.10/arch/arm/configs/mse500_defconfig cp -r -v linux-2.6.10/arch/arm/mach-spc2XXc \ linux-2.6.10/arch/arm/mach-mse500 cp -r -v linux-2.6.10/include/asm-arm/arch-spc2XXc \ linux-2.6.10/include/asm-arm/arch-mse500 cp devkit/rtai-3.1-2.6/rtai-core/arch/arm/hal/mach-spc2XXc/spc2XXc-timer.c \ devkit/rtai-3.1-2.6/rtai-core/arch/arm/hal/mach-mse500/mse500-timer.c cp -r -v devkit/rtai-3.1-2.6/rtai-core/include/asm-arm/arch-spc2XXc \ devkit/rtai-3.1-2.6/rtai-core/include/asm-arm/arch-mse500 cp devkit/plc-polux/timer/utmo_lisa.c devkit/plc-polux/timer/utmo_mse500.c
Diffstat (limited to 'polux/linux-2.6.10/arch/arm')
-rw-r--r--polux/linux-2.6.10/arch/arm/boot/compressed/head-mse500.S20
-rw-r--r--polux/linux-2.6.10/arch/arm/configs/mse500_defconfig796
-rw-r--r--polux/linux-2.6.10/arch/arm/mach-mse500/Kconfig14
-rw-r--r--polux/linux-2.6.10/arch/arm/mach-mse500/Makefile12
-rw-r--r--polux/linux-2.6.10/arch/arm/mach-mse500/Makefile.boot20
-rw-r--r--polux/linux-2.6.10/arch/arm/mach-mse500/core.c569
-rw-r--r--polux/linux-2.6.10/arch/arm/mach-mse500/entry-macro.S68
-rw-r--r--polux/linux-2.6.10/arch/arm/mach-mse500/fiq.S61
-rw-r--r--polux/linux-2.6.10/arch/arm/mach-mse500/generic.h34
-rw-r--r--polux/linux-2.6.10/arch/arm/mach-mse500/gpio.c76
-rw-r--r--polux/linux-2.6.10/arch/arm/mach-mse500/nvram.c82
-rw-r--r--polux/linux-2.6.10/arch/arm/mach-mse500/time.c155
12 files changed, 1907 insertions, 0 deletions
diff --git a/polux/linux-2.6.10/arch/arm/boot/compressed/head-mse500.S b/polux/linux-2.6.10/arch/arm/boot/compressed/head-mse500.S
new file mode 100644
index 0000000000..329167d8d3
--- /dev/null
+++ b/polux/linux-2.6.10/arch/arm/boot/compressed/head-mse500.S
@@ -0,0 +1,20 @@
+/*
+ * linux/arch/arm/boot/compressed/head-at91rm9200.S
+ *
+ * Copyright (C) 2003 SAN People
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+
+#include <linux/config.h>
+#include <asm/mach-types.h>
+
+ .section ".start", "ax"
+
+#ifdef CONFIG_MACH_SPC2XXC
+ ldr r7, =MACH_TYPE_SPC2XXC
+#endif
diff --git a/polux/linux-2.6.10/arch/arm/configs/mse500_defconfig b/polux/linux-2.6.10/arch/arm/configs/mse500_defconfig
new file mode 100644
index 0000000000..dbc4db0382
--- /dev/null
+++ b/polux/linux-2.6.10/arch/arm/configs/mse500_defconfig
@@ -0,0 +1,796 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.10-spk2xx
+# Wed Jul 9 09:58:45 2008
+#
+CONFIG_ARM=y
+# CONFIG_MMU is not set
+# CONFIG_MPU is not set
+CONFIG_NO_MU=y
+CONFIG_UID16=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+CONFIG_GENERIC_IOMAP=y
+
+#
+# Code maturity level options
+#
+CONFIG_EXPERIMENTAL=y
+# CONFIG_CLEAN_COMPILE is not set
+CONFIG_BROKEN=y
+CONFIG_BROKEN_ON_SMP=y
+
+#
+# General setup
+#
+CONFIG_RTHAL=y
+CONFIG_LOCALVERSION=""
+# CONFIG_POSIX_MQUEUE is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+CONFIG_SYSCTL=y
+# CONFIG_AUDIT is not set
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_HOTPLUG is not set
+# CONFIG_KOBJECT_UEVENT is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_EMBEDDED=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+# CONFIG_FUTEX is not set
+# CONFIG_EPOLL is not set
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_CC_ALIGN_FUNCTIONS=0
+CONFIG_CC_ALIGN_LABELS=0
+CONFIG_CC_ALIGN_LOOPS=0
+CONFIG_CC_ALIGN_JUMPS=0
+
+#
+# Loadable module support
+#
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+CONFIG_OBSOLETE_MODPARM=y
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+# CONFIG_KMOD is not set
+
+#
+# System Type
+#
+
+# CONFIG_ARCH_SPC200E is not set
+CONFIG_ARCH_SPC200C=y
+
+CONFIG_SET_MEM_PARAM=y
+CONFIG_DRAM_BASE=0xB0000000
+CONFIG_DRAM_SIZE=0x02000000
+CONFIG_FLASH_MEM_BASE=0x08000000
+CONFIG_FLASH_SIZE=0x00800000
+# CONFIG_FCM3 is not set
+CONFIG_MONA=y
+
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_ARM926T=y
+CONFIG_CPU_32v5=y
+CONFIG_CPU_ABRT_EV5TJ=y
+
+#
+# Processor Features
+#
+# CONFIG_ARM_THUMB is not set
+CONFIG_CPU_MXU_ENABLE=y
+CONFIG_CPU_RO_SRAM=y
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
+# CONFIG_CPU_CACHE_ROUND_ROBIN is not set
+# CONFIG_CPU_HIGH_VECTORS is not set
+
+#
+# General setup
+#
+CONFIG_ARM_AMBA=y
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+# CONFIG_XIP_KERNEL is not set
+
+#
+# At least one math emulation must be selected
+#
+# CONFIG_FPE_NWFPE is not set
+# CONFIG_FPE_FASTFPE is not set
+# CONFIG_VFP is not set
+CONFIG_BINFMT_FLAT=y
+CONFIG_BINFMT_ZFLAT=y
+# CONFIG_BINFMT_SHARED_FLAT is not set
+# CONFIG_BINFMT_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+# CONFIG_KERNEL_GZIP is not set
+CONFIG_KERNEL_LZMA=y
+
+#
+# Generic Driver Options
+#
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+# CONFIG_PM is not set
+CONFIG_LARGE_ALLOCS=y
+# CONFIG_PREEMPT is not set
+# CONFIG_ARTHUR is not set
+CONFIG_CMDLINE="console=ttyS0,115200n8"
+# CONFIG_LEDS is not set
+CONFIG_ALIGNMENT_TRAP=y
+
+#
+# Parallel port support
+#
+# CONFIG_PARPORT is not set
+
+#
+# Memory Technology Devices (MTD)
+#
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_CONCAT is not set
+# CONFIG_MTD_REDBOOT_PARTS is not set
+# CONFIG_MTD_CMDLINE_PARTS is not set
+# CONFIG_MTD_AFS_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=y
+CONFIG_MTD_CFI_ADV_OPTIONS=y
+CONFIG_MTD_CFI_NOSWAP=y
+# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
+# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set
+CONFIG_MTD_CFI_GEOMETRY=y
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+# CONFIG_MTD_MAP_BANK_WIDTH_2 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_4 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+# CONFIG_MTD_CFI_I2 is not set
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+CONFIG_MTD_CFI_INTELEXT=y
+CONFIG_MTD_CFI_AMDSTD=y
+CONFIG_MTD_CFI_AMDSTD_RETRY=0
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=y
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+# CONFIG_MTD_OBSOLETE_CHIPS is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+# CONFIG_MTD_PHYSMAP is not set
+# CONFIG_MTD_ARM_INTEGRATOR is not set
+# CONFIG_MTD_EDB7312 is not set
+# CONFIG_MTD_UCLINUX is not set
+# CONFIG_MTD_FCM3 is not set
+CONFIG_MTD_MONA=y
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLKMTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+
+#
+# NAND Flash Device Drivers
+#
+# CONFIG_MTD_NAND is not set
+
+#
+# Plug and Play support
+#
+
+#
+# Block devices
+#
+# CONFIG_BLK_DEV_FD is not set
+# CONFIG_BLK_DEV_LOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_RAM is not set
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_INITRAMFS_SOURCE="../package/initramfs/initramfs_list"
+# CONFIG_CDROM_PKTCDVD is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+# CONFIG_IOSCHED_AS is not set
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_IOSCHED_CFQ is not set
+
+#
+# Multi-device support (RAID and LVM)
+#
+# CONFIG_MD is not set
+
+#
+# Networking support
+#
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+# CONFIG_NETLINK_DEV is not set
+CONFIG_UNIX=y
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+# CONFIG_IP_ADVANCED_ROUTER is not set
+# CONFIG_IP_PNP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_IP_MROUTE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_TUNNEL is not set
+# CONFIG_IP_TCPDIAG is not set
+# CONFIG_IP_TCPDIAG_IPV6 is not set
+
+#
+# IP: Virtual Server Configuration
+#
+# CONFIG_IP_VS is not set
+CONFIG_IPV6=y
+CONFIG_IPV6_PRIVACY=y
+CONFIG_INET6_AH=y
+CONFIG_INET6_ESP=y
+CONFIG_INET6_IPCOMP=y
+CONFIG_INET6_TUNNEL=y
+CONFIG_IPV6_TUNNEL=y
+CONFIG_NETFILTER=y
+# CONFIG_NETFILTER_DEBUG is not set
+# CONFIG_BRIDGE_NETFILTER is not set
+
+#
+# IP: Netfilter Configuration
+#
+# CONFIG_IP_NF_CONNTRACK is not set
+# CONFIG_IP_NF_CONNTRACK_MARK is not set
+# CONFIG_IP_NF_QUEUE is not set
+CONFIG_IP_NF_IPTABLES=y
+CONFIG_IP_NF_MATCH_LIMIT=y
+CONFIG_IP_NF_MATCH_IPRANGE=y
+CONFIG_IP_NF_MATCH_MAC=y
+CONFIG_IP_NF_MATCH_PKTTYPE=y
+CONFIG_IP_NF_MATCH_MARK=y
+CONFIG_IP_NF_MATCH_MULTIPORT=y
+CONFIG_IP_NF_MATCH_TOS=y
+CONFIG_IP_NF_MATCH_RECENT=y
+# CONFIG_IP_NF_MATCH_ECN is not set
+CONFIG_IP_NF_MATCH_DSCP=y
+# CONFIG_IP_NF_MATCH_AH_ESP is not set
+CONFIG_IP_NF_MATCH_LENGTH=y
+# CONFIG_IP_NF_MATCH_TTL is not set
+# CONFIG_IP_NF_MATCH_TCPMSS is not set
+CONFIG_IP_NF_MATCH_OWNER=y
+CONFIG_IP_NF_MATCH_ADDRTYPE=y
+# CONFIG_IP_NF_MATCH_REALM is not set
+# CONFIG_IP_NF_MATCH_SCTP is not set
+# CONFIG_IP_NF_MATCH_COMMENT is not set
+# CONFIG_IP_NF_MATCH_HASHLIMIT is not set
+CONFIG_IP_NF_FILTER=y
+CONFIG_IP_NF_TARGET_REJECT=y
+# CONFIG_IP_NF_TARGET_LOG is not set
+# CONFIG_IP_NF_TARGET_ULOG is not set
+# CONFIG_IP_NF_TARGET_TCPMSS is not set
+CONFIG_IP_NF_MANGLE=y
+CONFIG_IP_NF_TARGET_TOS=y
+# CONFIG_IP_NF_TARGET_ECN is not set
+CONFIG_IP_NF_TARGET_DSCP=y
+CONFIG_IP_NF_TARGET_MARK=y
+CONFIG_IP_NF_TARGET_CLASSIFY=y
+# CONFIG_IP_NF_RAW is not set
+# CONFIG_IP_NF_ARPTABLES is not set
+
+#
+# IPv6: Netfilter Configuration
+#
+# CONFIG_IP6_NF_QUEUE is not set
+# CONFIG_IP6_NF_IPTABLES is not set
+
+#
+# Bridge: Netfilter Configuration
+#
+CONFIG_BRIDGE_NF_EBTABLES=y
+CONFIG_BRIDGE_EBT_BROUTE=y
+CONFIG_BRIDGE_EBT_T_FILTER=y
+CONFIG_BRIDGE_EBT_T_NAT=y
+CONFIG_BRIDGE_EBT_802_3=y
+CONFIG_BRIDGE_EBT_AMONG=y
+CONFIG_BRIDGE_EBT_ARP=y
+CONFIG_BRIDGE_EBT_IP=y
+CONFIG_BRIDGE_EBT_LIMIT=y
+CONFIG_BRIDGE_EBT_PLC=m
+CONFIG_BRIDGE_EBT_MARK=y
+CONFIG_BRIDGE_EBT_PKTTYPE=y
+CONFIG_BRIDGE_EBT_STP=y
+CONFIG_BRIDGE_EBT_VLAN=y
+CONFIG_BRIDGE_EBT_ARPREPLY=y
+CONFIG_BRIDGE_EBT_DNAT=y
+CONFIG_BRIDGE_EBT_MARK_T=y
+CONFIG_BRIDGE_EBT_REDIRECT=y
+CONFIG_BRIDGE_EBT_SNAT=y
+CONFIG_BRIDGE_EBT_LOG=y
+CONFIG_XFRM=y
+# CONFIG_XFRM_USER is not set
+
+#
+# SCTP Configuration (EXPERIMENTAL)
+#
+# CONFIG_IP_SCTP is not set
+# CONFIG_ATM is not set
+CONFIG_BRIDGE=y
+CONFIG_VLAN_8021Q=y
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_NET_DIVERT is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+
+#
+# QoS and/or fair queueing
+#
+CONFIG_NET_SCHED=y
+CONFIG_NET_SCH_CLK_JIFFIES=y
+# CONFIG_NET_SCH_CLK_GETTIMEOFDAY is not set
+# CONFIG_NET_SCH_CLK_CPU is not set
+CONFIG_NET_SCH_CBQ=y
+CONFIG_NET_SCH_HTB=y
+# CONFIG_NET_SCH_HFSC is not set
+CONFIG_NET_SCH_PRIO=y
+CONFIG_NET_SCH_RED=y
+CONFIG_NET_SCH_SFQ=y
+# CONFIG_NET_SCH_TEQL is not set
+CONFIG_NET_SCH_TBF=y
+# CONFIG_NET_SCH_GRED is not set
+CONFIG_NET_SCH_DSMARK=y
+# CONFIG_NET_SCH_NETEM is not set
+CONFIG_NET_SCH_INGRESS=y
+CONFIG_NET_QOS=y
+CONFIG_NET_ESTIMATOR=y
+CONFIG_NET_CLS=y
+CONFIG_NET_CLS_TCINDEX=y
+CONFIG_NET_CLS_ROUTE4=y
+CONFIG_NET_CLS_ROUTE=y
+CONFIG_NET_CLS_FW=y
+CONFIG_NET_CLS_U32=y
+# CONFIG_CLS_U32_PERF is not set
+# CONFIG_NET_CLS_IND is not set
+# CONFIG_NET_CLS_RSVP is not set
+# CONFIG_NET_CLS_RSVP6 is not set
+# CONFIG_NET_CLS_ACT is not set
+CONFIG_NET_CLS_POLICE=y
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+CONFIG_NETDEVICES=y
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+
+#
+# Ethernet (10 or 100Mbit)
+#
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+CONFIG_KS8001=y
+CONFIG_KS8001_NAPI=y
+# CONFIG_KS8001_RMII is not set
+# CONFIG_NET_VENDOR_SMC is not set
+# CONFIG_SMC91X is not set
+# CONFIG_NE2000 is not set
+
+#
+# Ethernet (1000 Mbit)
+#
+
+#
+# Ethernet (10000 Mbit)
+#
+
+#
+# Token Ring devices
+#
+
+#
+# Wireless LAN (non-hamradio)
+#
+# CONFIG_NET_RADIO is not set
+
+#
+# Wan interfaces
+#
+# CONFIG_WAN is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_SHAPER is not set
+# CONFIG_NETCONSOLE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_SCSI is not set
+
+#
+# Fusion MPT device support
+#
+
+#
+# IEEE 1394 (FireWire) support
+#
+# CONFIG_IEEE1394 is not set
+
+#
+# I2O device support
+#
+
+#
+# ISDN subsystem
+#
+# CONFIG_ISDN is not set
+
+#
+# Input device support
+#
+# CONFIG_INPUT is not set
+
+#
+# Userland interfaces
+#
+
+#
+# Input I/O drivers
+#
+# CONFIG_GAMEPORT is not set
+CONFIG_SOUND_GAMEPORT=y
+# CONFIG_SERIO is not set
+
+#
+# Input Device Drivers
+#
+
+#
+# Character devices
+#
+# CONFIG_VT is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_SPC2XXC=y
+CONFIG_SERIAL_SPC2XXC_CONSOLE=y
+# CONFIG_UART_FIQ is not set
+# CONFIG_SERIAL_T32 is not set
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=16
+
+#
+# IPMI
+#
+# CONFIG_IPMI_HANDLER is not set
+
+#
+# Watchdog Cards
+#
+CONFIG_WATCHDOG=y
+# CONFIG_WATCHDOG_NOWAYOUT is not set
+
+#
+# Watchdog Device Drivers
+#
+# CONFIG_SOFT_WATCHDOG is not set
+# CONFIG_SPR200_WATCHDOG is not set
+# CONFIG_NVRAM is not set
+# CONFIG_RTC is not set
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+
+#
+# Ftape, the floppy tape device driver
+#
+# CONFIG_DRM is not set
+# CONFIG_RAW_DRIVER is not set
+
+#
+# I2C support
+#
+# CONFIG_I2C is not set
+
+#
+# File systems
+#
+# CONFIG_EXT2_FS is not set
+# CONFIG_EXT3_FS is not set
+# CONFIG_JBD is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_QUOTA is not set
+# CONFIG_DNOTIFY is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+# CONFIG_MSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_SYSFS=y
+# CONFIG_DEVFS_FS is not set
+# CONFIG_DEVPTS_FS_XATTR is not set
+# CONFIG_TMPFS is not set
+# CONFIG_HUGETLBFS is not set
+# CONFIG_HUGETLB_PAGE is not set
+CONFIG_RAMFS=y
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_JFFS_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+# CONFIG_JFFS2_FS_NAND is not set
+# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
+CONFIG_JFFS2_ZLIB=y
+CONFIG_JFFS2_RTIME=y
+# CONFIG_JFFS2_RUBIN is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+
+#
+# Network File Systems
+#
+# CONFIG_NFS_FS is not set
+# CONFIG_NFSD is not set
+# CONFIG_EXPORTFS is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+
+#
+# Native Language Support
+#
+CONFIG_NLS=m
+CONFIG_NLS_DEFAULT="iso8859-1"
+# CONFIG_NLS_CODEPAGE_437 is not set
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ASCII is not set
+# CONFIG_NLS_ISO8859_1 is not set
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
+
+#
+# Misc devices
+#
+
+#
+# USB support
+#
+# CONFIG_USB is not set
+CONFIG_USB_ARCH_HAS_HCD=y
+# CONFIG_USB_ARCH_HAS_OHCI is not set
+
+#
+# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information
+#
+
+#
+# USB Gadget Support
+#
+# CONFIG_USB_GADGET is not set
+
+#
+# MMC/SD Card support
+#
+# CONFIG_MMC is not set
+
+#
+# PLC support
+#
+CONFIG_PLC=y
+# CONFIG_SLAVE is not set
+# CONFIG_PLC_MEASURES is not set
+# CONFIG_PLC_DEBUG is not set
+# CONFIG_PLC_PPC is not set
+# CONFIG_PLC_ASSERT is not set
+# CONFIG_PLC_RTALLOC_DEBUG is not set
+# CONFIG_PLC_SKBALLOC_DEBUG is not set
+# CONFIG_PLC_GDB is not set
+# CONFIG_PLC_DEBUG_GPIO is not set
+# CONFIG_PLC_PROFILER is not set
+# CONFIG_PLC_HELPER_SCRIPTS is not set
+
+#
+# Extended Features
+#
+# CONFIG_PLC_PCI is not set
+CONFIG_PLC_TIMEOUT=y
+CONFIG_PLC_MCAST=m
+# CONFIG_PLC_CRYPTO is not set
+CONFIG_PLC_NEWPHLIC=y
+# CONFIG_PLC_EVENT_NOTIFICATION is not set
+
+#
+# VoIP support
+#
+# CONFIG_VOIP is not set
+# CONFIG_ARETHA is not set
+# CONFIG_INTEL_BUS is not set
+
+#
+# Kernel hacking
+#
+# CONFIG_DEBUG_KERNEL is not set
+# CONFIG_DEBUG_INFO is not set
+# CONFIG_FRAME_POINTER is not set
+# CONFIG_DEBUG_USER is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+
+#
+# Cryptographic options
+#
+CONFIG_CRYPTO=y
+CONFIG_CRYPTO_HMAC=y
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_MD4 is not set
+CONFIG_CRYPTO_MD5=y
+CONFIG_CRYPTO_SHA1=y
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_WP512 is not set
+CONFIG_CRYPTO_DES=y
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_AES is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_ARC4 is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_ANUBIS is not set
+CONFIG_CRYPTO_DEFLATE=y
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Library routines
+#
+CONFIG_CRC_CCITT=y
+CONFIG_CRC32=y
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
diff --git a/polux/linux-2.6.10/arch/arm/mach-mse500/Kconfig b/polux/linux-2.6.10/arch/arm/mach-mse500/Kconfig
new file mode 100644
index 0000000000..5bf788827e
--- /dev/null
+++ b/polux/linux-2.6.10/arch/arm/mach-mse500/Kconfig
@@ -0,0 +1,14 @@
+if ARCH_SPC200C
+
+choice
+ prompt "SPC200c platform version"
+ default MONA
+
+config MONA
+ bool "Support GLORIA/MONA based platforms"
+ help
+ Include support for SPiDCOM Mona Lisa development board platform.
+
+endchoice
+
+endif
diff --git a/polux/linux-2.6.10/arch/arm/mach-mse500/Makefile b/polux/linux-2.6.10/arch/arm/mach-mse500/Makefile
new file mode 100644
index 0000000000..f216546b57
--- /dev/null
+++ b/polux/linux-2.6.10/arch/arm/mach-mse500/Makefile
@@ -0,0 +1,12 @@
+#
+# Makefile for the linux kernel.
+#
+
+
+obj-y := time.o gpio.o
+obj-m :=
+obj-n :=
+obj- :=
+
+obj-$(CONFIG_ARCH_SPC200C) += core.o
+obj-$(CONFIG_MONA) += nvram.o
diff --git a/polux/linux-2.6.10/arch/arm/mach-mse500/Makefile.boot b/polux/linux-2.6.10/arch/arm/mach-mse500/Makefile.boot
new file mode 100644
index 0000000000..505e4d0be9
--- /dev/null
+++ b/polux/linux-2.6.10/arch/arm/mach-mse500/Makefile.boot
@@ -0,0 +1,20 @@
+# Note: the following conditions must always be true:
+# ZRELADDR == virt_to_phys(TEXTADDR)
+# PARAMS_PHYS must be within 4MB of ZRELADDR
+# INITRD_PHYS must be in RAM
+
+#zreladdr-y := 0x88008000
+#params_phys-y := 0x88000100
+#initrd_phys-y := 0x8f000000
+
+#zreladdr-y := 0xa0008000
+#params_phys-y := 0xa0000100
+#initrd_phys-y := 0xaf000000
+
+#zreladdr-y := 0xa4008000
+#params_phys-y := 0xa4000100
+#initrd_phys-y := 0xa5000000
+
+zreladdr-y := 0xb0008000
+params_phys-y := 0xb0000100
+initrd_phys-y := 0xb1000000
diff --git a/polux/linux-2.6.10/arch/arm/mach-mse500/core.c b/polux/linux-2.6.10/arch/arm/mach-mse500/core.c
new file mode 100644
index 0000000000..19acc82781
--- /dev/null
+++ b/polux/linux-2.6.10/arch/arm/mach-mse500/core.c
@@ -0,0 +1,569 @@
+/*
+ * arch/arm/mach-spc2XXc/core.c
+ *
+ * (C) Copyright 2007 SPiDCOM Technologies
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <linux/config.h>
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/mm.h>
+#include <linux/module.h>
+
+#include <asm/sizes.h>
+#include <asm/hardware.h>
+#include <asm/setup.h>
+#include <asm/mach-types.h>
+#include <asm/irq.h>
+#include <asm/fiq.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/irq.h>
+
+#include <asm/arch/hardware.h>
+#include "generic.h"
+#include "platform.h"
+
+#ifdef CONFIG_CPU_MXU_ENABLE
+#include <asm/cachezone.h>
+#endif
+
+typedef struct
+{
+ uint32_t SDRAM_size;
+ uint32_t Flash_size;
+ uint8_t Wd_gpio;
+ uint8_t Rst_gpio;
+ uint16_t spare0;
+ uint32_t spare1;
+} __attribute__ ((__packed__)) board_spec_t;
+
+#define DEFAULT_SDRAM_SIZE 0x02000000 // 32MB by default
+#define BOARD_SPEC_ADDR 0x00000fe0
+
+uint32_t SDRAM_size = DEFAULT_SDRAM_SIZE;
+uint32_t DMA_zone_base;
+
+static int spc2XXc_global_mode = 0;
+//static unsigned int spc2XXc_FPGA_clock = 66666666;
+static unsigned int spc2XXc_FPGA_clock = EXT_APB_CLK;
+
+void spc2XXc_register_uart(int idx, int port);
+
+#ifdef CONFIG_MMU
+static struct map_desc spc2XXc_periph_internal_desc[] __initdata = {
+ { INT_APB_VIRT_BASE, INT_APB_BASE, SZ_1M, MT_DEVICE}
+}; /* spc2XXc_periph_internal_desc */
+
+static struct map_desc spc2XXc_apb_periph_external_desc[] __initdata = {
+ /* virtual, physical, length, type */
+ { EXT_AHBM0_APBVIRT_BASE, EXT_AHBM0_APB_BASE, SZ_2M, MT_DEVICE}
+}; /* spc2XXc_apb_periph_external_desc */
+
+static struct map_desc spc2XXc_ahbeth_periph_external_desc[] __initdata = {
+ /* virtual, physical, length, type */
+ { EXT_AHBM0_AHB_ETHVIRT_BASE, EXT_AHBM0_AHB_ETH_BASE, SZ_1M, MT_DEVICE}
+}; /* spc2XXc_ahbeth_periph_external_desc */
+
+static struct map_desc spc2XXc_ahbplc_periph_external_desc[] __initdata = {
+ /* virtual, physical, length, type */
+ { EXT_AHBM0_AHB_PLCVIRT_BASE, EXT_AHBM0_AHB_PLC_BASE, SZ_16M, MT_DEVICE}
+}; /* spc2XXc_ahbplc_periph_external_desc */
+#endif
+
+#ifdef CONFIG_CPU_MXU_ENABLE
+// 1GB of SDRAM is allocated cached
+// the pages will be turned to error
+// in the fixup function.
+struct cache_zone_t cache_zones[16] =
+ {
+ { 0x00000000, 0xF0000000, AM_ERROR },
+ { 0xF0000000, 0x10000000, AM_ERROR },
+ { SRAM_BASE, 0x00100000, AM_UNCACHED },
+// { SRAM_BASE, 0x00100000, AM_WRITEBACK },
+ { FLASH_BASE, FLASH_SIZE, AM_UNCACHED },
+ { EXT_AHBM0_APB_BASE, 0x00200000, AM_UNCACHED },
+ { EXT_AHBM0_AHB_ETH_BASE, 0x00010000, AM_UNCACHED },
+ { SDRAM_CFG_BASE, 0x00100000, AM_UNCACHED },
+ { EXT_AHBM0_AHB_PLC_BASE, 0x01000000, AM_UNCACHED },
+ { SDRAM_BASE, 0x10000000, AM_WRITEBACK },
+ { INT_APB_BASE, 0x00100000, AM_UNCACHED },
+ { 0xffffffff } // END UP WITH THIS
+ };
+#endif
+
+struct gic_lines {
+ const char *name;
+#ifdef CONFIG_UART_FIQ
+ unsigned char sdi; // 0 is IRQ, 1 is FIQ
+#endif
+ unsigned char prior;
+ unsigned char type;
+}; /* gic_lines */
+
+/* PRIOR_0 is the most lowest interruption. */
+/* PRIOR_7 is the most highest interruption. */
+#ifdef CONFIG_UART_FIQ
+static struct gic_lines spc2XXc_irq_lines[NR_IRQS] = {
+ /* 0 */ { "-" , SDI_IRQ, PRIOR_0, SRCTYPE_POSITIVE_EDGE_TRIGGERED },
+ /* 1 */ { "ETHERNET" , SDI_IRQ, PRIOR_1, SRCTYPE_POSITIVE_EDGE_TRIGGERED },
+ /* 2 */ { "OS Timer" , SDI_IRQ, PRIOR_7, SRCTYPE_POSITIVE_EDGE_TRIGGERED }, // Timer linux
+ /* 3 */ { "ST1" , SDI_IRQ, PRIOR_3, SRCTYPE_POSITIVE_EDGE_TRIGGERED }, // old interruption use for utmo. hardware bugge
+ /* 4 */ { "ST2" , SDI_IRQ, PRIOR_0, SRCTYPE_POSITIVE_EDGE_TRIGGERED },
+ /* 5 */ { "ST3" , SDI_IRQ, PRIOR_0, SRCTYPE_POSITIVE_EDGE_TRIGGERED },
+ /* 6 */ { "-" , SDI_IRQ, PRIOR_0, SRCTYPE_POSITIVE_EDGE_TRIGGERED },
+ /* 7 */ { "PIO" , SDI_IRQ, PRIOR_0, SRCTYPE_HIGH_LEVEL_SENSITIVE },
+ /* 8 */ { "MPIO" , SDI_IRQ, PRIOR_0, SRCTYPE_HIGH_LEVEL_SENSITIVE },
+ /* 9 */ { "EBI_PIO" , SDI_IRQ, PRIOR_0, SRCTYPE_HIGH_LEVEL_SENSITIVE },
+ /* 10 */ { "-" , SDI_IRQ, PRIOR_0, SRCTYPE_HIGH_LEVEL_SENSITIVE },
+ /* 11 */ { "PLC_INT__RX_END" , SDI_IRQ, PRIOR_4, SRCTYPE_POSITIVE_EDGE_TRIGGERED },
+ /* 12 */ { "PLC_PHLIC" , SDI_IRQ, PRIOR_0, SRCTYPE_POSITIVE_EDGE_TRIGGERED },
+ /* 13 */ { "PLC_ERROR" , SDI_IRQ, PRIOR_0, SRCTYPE_POSITIVE_EDGE_TRIGGERED },
+ /* 14 */ { "TEST_IRQ_VECTOR" , SDI_IRQ, PRIOR_2, SRCTYPE_POSITIVE_EDGE_TRIGGERED }, // IRQ software (virtual)
+ /* 15 */ { "PLC_INT__MAC_LAYER", SDI_IRQ, PRIOR_2, SRCTYPE_POSITIVE_EDGE_TRIGGERED }, // Virtual IRQs
+ /* 16 */ { "Taked_by_Serial" , SDI_FIQ, PRIOR_7, SRCTYPE_POSITIVE_EDGE_TRIGGERED },
+ /* 17 */ { "UTMO" , SDI_IRQ, PRIOR_3, SRCTYPE_POSITIVE_EDGE_TRIGGERED }, // IRQ software (virtual)
+ /* 18 */ { "USART0" , SDI_IRQ, PRIOR_0, SRCTYPE_POSITIVE_EDGE_TRIGGERED }, // See spc200-e
+ /* 19 */ { "MAC_Layer" , SDI_IRQ, PRIOR_2, SRCTYPE_POSITIVE_EDGE_TRIGGERED }, // See spc200-e
+ /* 20 */ { "PLC_INT_PHLIC__RX_BUSY", SDI_IRQ, PRIOR_5, SRCTYPE_POSITIVE_EDGE_TRIGGERED },/*pmd_set_busy_irq(2);*/
+ /* 21 */ { "PLC_INT_PHLIC__RX_CTRL", SDI_IRQ, PRIOR_4, SRCTYPE_POSITIVE_EDGE_TRIGGERED },/*pmd_set_rx_start_irq(3);*/
+ /* 22 */ { "PLC_INT_PHLIC__RX_DATA", SDI_IRQ, PRIOR_4, SRCTYPE_POSITIVE_EDGE_TRIGGERED },/*pmd_set_rx_data_irq(4);*/
+ /* 23 */ { "PLC_INT_PHLIC__RX_EOF", SDI_IRQ, PRIOR_4, SRCTYPE_POSITIVE_EDGE_TRIGGERED },/*pmd_set_eof_irq(5);*/
+ /* 24 */ { "PLC_INT_PHLIC__TX_END", SDI_IRQ, PRIOR_6, SRCTYPE_POSITIVE_EDGE_TRIGGERED },/*pmd_set_tx_end_irq(6);*/
+ /* 25 */ { "PLC_PHLIC_7" , SDI_IRQ, PRIOR_2, SRCTYPE_POSITIVE_EDGE_TRIGGERED },/*pmd_set_tx_data_irq(7);*/
+ /* 26 */ { "PLC_INT_PHLIC__TX_CTRL", SDI_IRQ, PRIOR_6, SRCTYPE_POSITIVE_EDGE_TRIGGERED },/*pmd_set_tx_more_irq(8);*/
+ /* 27 */ { "PLC_INT_PHLIC__TMO1", SDI_IRQ, PRIOR_3, SRCTYPE_POSITIVE_EDGE_TRIGGERED },/*pmd_set_tmo1_irq(9);*/
+ /* 28 */ { "PLC_INT_PHLIC__TMO2", SDI_IRQ, PRIOR_3, SRCTYPE_POSITIVE_EDGE_TRIGGERED },/*pmd_set_tmo2_irq(10);*/
+ /* 29 */ { "PLC_PHLIC_11" , SDI_IRQ, PRIOR_3, SRCTYPE_POSITIVE_EDGE_TRIGGERED },/*pmd_set_tmo3_irq(11);*/
+ /* 30 */ { "POLL_IRQ" , SDI_IRQ, PRIOR_2, SRCTYPE_POSITIVE_EDGE_TRIGGERED },
+ /* 31 */ { "R2L_IRQ" , SDI_IRQ, PRIOR_2, SRCTYPE_POSITIVE_EDGE_TRIGGERED },
+ /* 32 */ { "-" , SDI_IRQ, PRIOR_0, SRCTYPE_POSITIVE_EDGE_TRIGGERED },
+ /* 33 */ { "-" , SDI_IRQ, PRIOR_0, SRCTYPE_POSITIVE_EDGE_TRIGGERED },
+ /* 34 */ { "-" , SDI_IRQ, PRIOR_0, SRCTYPE_POSITIVE_EDGE_TRIGGERED },
+ /* 35 */ { "-" , SDI_IRQ, PRIOR_0, SRCTYPE_POSITIVE_EDGE_TRIGGERED },
+ /* 36 */ { "-" , SDI_IRQ, PRIOR_0, SRCTYPE_POSITIVE_EDGE_TRIGGERED },
+ /* 37 */ { "-" , SDI_IRQ, PRIOR_0, SRCTYPE_POSITIVE_EDGE_TRIGGERED },
+ /* 38 */ { "-" , SDI_IRQ, PRIOR_0, SRCTYPE_POSITIVE_EDGE_TRIGGERED },
+ /* 39 */ { "-" , SDI_IRQ, PRIOR_0, SRCTYPE_POSITIVE_EDGE_TRIGGERED },
+ /* 40 */ { "-" , SDI_IRQ, PRIOR_0, SRCTYPE_POSITIVE_EDGE_TRIGGERED },
+ /* 41 */ { "-" , SDI_IRQ, PRIOR_0, SRCTYPE_POSITIVE_EDGE_TRIGGERED },
+ /* 42 */ { "-" , SDI_IRQ, PRIOR_0, SRCTYPE_POSITIVE_EDGE_TRIGGERED },
+ /* 43 */ { "-" , SDI_IRQ, PRIOR_0, SRCTYPE_POSITIVE_EDGE_TRIGGERED },
+ /* 44 */ { "-" , SDI_IRQ, PRIOR_0, SRCTYPE_POSITIVE_EDGE_TRIGGERED },
+ /* 45 */ { "-" , SDI_IRQ, PRIOR_0, SRCTYPE_POSITIVE_EDGE_TRIGGERED },
+ /* 46 */ { "-" , SDI_IRQ, PRIOR_0, SRCTYPE_POSITIVE_EDGE_TRIGGERED },
+ /* 47 */ { "-" , SDI_IRQ, PRIOR_0, SRCTYPE_POSITIVE_EDGE_TRIGGERED },
+ /* 48 */ { "-" , SDI_IRQ, PRIOR_0, SRCTYPE_POSITIVE_EDGE_TRIGGERED },
+ /* 49 */ { "-" , SDI_IRQ, PRIOR_0, SRCTYPE_POSITIVE_EDGE_TRIGGERED },
+ /* 50 */ { "-" , SDI_IRQ, PRIOR_0, SRCTYPE_POSITIVE_EDGE_TRIGGERED },
+ /* 51 */ { "-" , SDI_IRQ, PRIOR_0, SRCTYPE_POSITIVE_EDGE_TRIGGERED },
+ /* 52 */ { "-" , SDI_IRQ, PRIOR_0, SRCTYPE_POSITIVE_EDGE_TRIGGERED },
+ /* 53 */ { "-" , SDI_IRQ, PRIOR_0, SRCTYPE_POSITIVE_EDGE_TRIGGERED },
+ /* 54 */ { "-" , SDI_IRQ, PRIOR_0, SRCTYPE_POSITIVE_EDGE_TRIGGERED },
+ /* 55 */ { "-" , SDI_IRQ, PRIOR_0, SRCTYPE_POSITIVE_EDGE_TRIGGERED },
+ /* 56 */ { "-" , SDI_IRQ, PRIOR_0, SRCTYPE_POSITIVE_EDGE_TRIGGERED },
+ /* 57 */ { "-" , SDI_IRQ, PRIOR_0, SRCTYPE_POSITIVE_EDGE_TRIGGERED },
+ /* 58 */ { "-" , SDI_IRQ, PRIOR_0, SRCTYPE_POSITIVE_EDGE_TRIGGERED },
+ /* 59 */ { "-" , SDI_IRQ, PRIOR_0, SRCTYPE_POSITIVE_EDGE_TRIGGERED },
+ /* 60 */ { "-" , SDI_IRQ, PRIOR_0, SRCTYPE_POSITIVE_EDGE_TRIGGERED },
+ /* 61 */ { "-" , SDI_IRQ, PRIOR_0, SRCTYPE_POSITIVE_EDGE_TRIGGERED },
+ /* 62 */ { "-" , SDI_IRQ, PRIOR_0, SRCTYPE_POSITIVE_EDGE_TRIGGERED },
+ /* 63 */ { "-" , SDI_IRQ, PRIOR_0, SRCTYPE_POSITIVE_EDGE_TRIGGERED },
+};
+#else
+static struct gic_lines spc2XXc_irq_lines[64] = {
+/* 0 */ { "-", PRIOR_0, SRCTYPE_POSITIVE_EDGE_TRIGGERED },
+/* 1 */ { "ETHERNET", PRIOR_1, SRCTYPE_POSITIVE_EDGE_TRIGGERED },
+/* 2 */ { "OS Timer", PRIOR_7, SRCTYPE_POSITIVE_EDGE_TRIGGERED }, // Timer linux
+/* 3 */ { "ST1", PRIOR_3, SRCTYPE_POSITIVE_EDGE_TRIGGERED }, // old interruption use for utmo. hardware bugge
+/* 4 */ { "ST2", PRIOR_0, SRCTYPE_POSITIVE_EDGE_TRIGGERED },
+/* 5 */ { "ST3", PRIOR_0, SRCTYPE_POSITIVE_EDGE_TRIGGERED },
+/* 6 */ { "-", PRIOR_0, SRCTYPE_POSITIVE_EDGE_TRIGGERED },
+/* 7 */ { "PIO", PRIOR_0, SRCTYPE_HIGH_LEVEL_SENSITIVE },
+/* 8 */ { "MPIO", PRIOR_0, SRCTYPE_HIGH_LEVEL_SENSITIVE },
+/* 9 */ { "EBI_PIO", PRIOR_0, SRCTYPE_HIGH_LEVEL_SENSITIVE },
+/* 10 */ { "-", PRIOR_0, SRCTYPE_HIGH_LEVEL_SENSITIVE },
+/* 11 */ { "PLC_INT__RX_END",PRIOR_4, SRCTYPE_POSITIVE_EDGE_TRIGGERED },
+/* 12 */ { "PLC_PHLIC", PRIOR_0, SRCTYPE_POSITIVE_EDGE_TRIGGERED },
+/* 13 */ { "PLC_ERROR", PRIOR_0, SRCTYPE_POSITIVE_EDGE_TRIGGERED },
+/* 14 */ { "TEST_IRQ_VECTOR", PRIOR_2, SRCTYPE_POSITIVE_EDGE_TRIGGERED }, // IRQ software (virtual)
+/* 15 */ { "PLC_INT__MAC_LAYER", PRIOR_2, SRCTYPE_POSITIVE_EDGE_TRIGGERED }, // Virtual IRQs
+/* 16 */ { "USART0", PRIOR_0, SRCTYPE_POSITIVE_EDGE_TRIGGERED },
+/* 17 */ { "UTMO", PRIOR_3, SRCTYPE_POSITIVE_EDGE_TRIGGERED }, // IRQ software (virtual)
+/* 18 */ { "-", PRIOR_0, SRCTYPE_POSITIVE_EDGE_TRIGGERED }, // See spc200-e
+/* 19 */ { "-", PRIOR_0, SRCTYPE_POSITIVE_EDGE_TRIGGERED }, // See spc200-e
+/* 20 */ { "PLC_INT_PHLIC__RX_BUSY", PRIOR_5, SRCTYPE_POSITIVE_EDGE_TRIGGERED },/*pmd_set_busy_irq(2);*/
+/* 21 */ { "PLC_INT_PHLIC__RX_CTRL", PRIOR_4, SRCTYPE_POSITIVE_EDGE_TRIGGERED },/*pmd_set_rx_start_irq(3);*/
+/* 22 */ { "PLC_INT_PHLIC__RX_DATA", PRIOR_4, SRCTYPE_POSITIVE_EDGE_TRIGGERED },/*pmd_set_rx_data_irq(4);*/
+/* 23 */ { "PLC_INT_PHLIC__RX_EOF", PRIOR_4, SRCTYPE_POSITIVE_EDGE_TRIGGERED },/*pmd_set_eof_irq(5);*/
+/* 24 */ { "PLC_INT_PHLIC__TX_END", PRIOR_6, SRCTYPE_POSITIVE_EDGE_TRIGGERED },/*pmd_set_tx_end_irq(6);*/
+/* 25 */ { "PLC_PHLIC_7", PRIOR_2, SRCTYPE_POSITIVE_EDGE_TRIGGERED },/*pmd_set_tx_data_irq(7);*/
+/* 26 */ { "PLC_INT_PHLIC__TX_CTRL", PRIOR_6, SRCTYPE_POSITIVE_EDGE_TRIGGERED },/*pmd_set_tx_more_irq(8);*/
+/* 27 */ { "PLC_INT_PHLIC__TMO1", PRIOR_3, SRCTYPE_POSITIVE_EDGE_TRIGGERED },/*pmd_set_tmo1_irq(9);*/
+/* 28 */ { "PLC_INT_PHLIC__TMO2", PRIOR_3, SRCTYPE_POSITIVE_EDGE_TRIGGERED },/*pmd_set_tmo2_irq(10);*/
+/* 29 */ { "PLC_PHLIC_11", PRIOR_3, SRCTYPE_POSITIVE_EDGE_TRIGGERED },/*pmd_set_tmo3_irq(11);*/
+/* 30 */ { "POLL_IRQ", PRIOR_2, SRCTYPE_POSITIVE_EDGE_TRIGGERED },
+/* 31 */ { "R2L_IRQ", PRIOR_2, SRCTYPE_POSITIVE_EDGE_TRIGGERED },
+/* 32 */ { "-", PRIOR_0, SRCTYPE_POSITIVE_EDGE_TRIGGERED },
+/* 33 */ { "-", PRIOR_0, SRCTYPE_POSITIVE_EDGE_TRIGGERED },
+/* 34 */ { "-", PRIOR_0, SRCTYPE_POSITIVE_EDGE_TRIGGERED },
+/* 35 */ { "-", PRIOR_0, SRCTYPE_POSITIVE_EDGE_TRIGGERED },
+/* 36 */ { "-", PRIOR_0, SRCTYPE_POSITIVE_EDGE_TRIGGERED },
+/* 37 */ { "-", PRIOR_0, SRCTYPE_POSITIVE_EDGE_TRIGGERED },
+/* 38 */ { "-", PRIOR_0, SRCTYPE_POSITIVE_EDGE_TRIGGERED },
+/* 39 */ { "-", PRIOR_0, SRCTYPE_POSITIVE_EDGE_TRIGGERED },
+/* 40 */ { "-", PRIOR_0, SRCTYPE_POSITIVE_EDGE_TRIGGERED },
+/* 41 */ { "-", PRIOR_0, SRCTYPE_POSITIVE_EDGE_TRIGGERED },
+/* 42 */ { "-", PRIOR_0, SRCTYPE_POSITIVE_EDGE_TRIGGERED },
+/* 43 */ { "-", PRIOR_0, SRCTYPE_POSITIVE_EDGE_TRIGGERED },
+/* 44 */ { "-", PRIOR_0, SRCTYPE_POSITIVE_EDGE_TRIGGERED },
+/* 45 */ { "-", PRIOR_0, SRCTYPE_POSITIVE_EDGE_TRIGGERED },
+/* 46 */ { "-", PRIOR_0, SRCTYPE_POSITIVE_EDGE_TRIGGERED },
+/* 47 */ { "-", PRIOR_0, SRCTYPE_POSITIVE_EDGE_TRIGGERED },
+/* 48 */ { "-", PRIOR_0, SRCTYPE_POSITIVE_EDGE_TRIGGERED },
+/* 49 */ { "-", PRIOR_0, SRCTYPE_POSITIVE_EDGE_TRIGGERED },
+/* 50 */ { "-", PRIOR_0, SRCTYPE_POSITIVE_EDGE_TRIGGERED },
+/* 51 */ { "-", PRIOR_0, SRCTYPE_POSITIVE_EDGE_TRIGGERED },
+/* 52 */ { "-", PRIOR_0, SRCTYPE_POSITIVE_EDGE_TRIGGERED },
+/* 53 */ { "-", PRIOR_0, SRCTYPE_POSITIVE_EDGE_TRIGGERED },
+/* 54 */ { "-", PRIOR_0, SRCTYPE_POSITIVE_EDGE_TRIGGERED },
+/* 55 */ { "-", PRIOR_0, SRCTYPE_POSITIVE_EDGE_TRIGGERED },
+/* 56 */ { "-", PRIOR_0, SRCTYPE_POSITIVE_EDGE_TRIGGERED },
+/* 57 */ { "-", PRIOR_0, SRCTYPE_POSITIVE_EDGE_TRIGGERED },
+/* 58 */ { "-", PRIOR_0, SRCTYPE_POSITIVE_EDGE_TRIGGERED },
+/* 59 */ { "-", PRIOR_0, SRCTYPE_POSITIVE_EDGE_TRIGGERED },
+/* 60 */ { "-", PRIOR_0, SRCTYPE_POSITIVE_EDGE_TRIGGERED },
+/* 61 */ { "-", PRIOR_0, SRCTYPE_POSITIVE_EDGE_TRIGGERED },
+/* 62 */ { "-", PRIOR_0, SRCTYPE_POSITIVE_EDGE_TRIGGERED },
+/* 63 */ { "-", PRIOR_0, SRCTYPE_POSITIVE_EDGE_TRIGGERED },
+};
+#endif
+
+
+/**
+ * Function: get_spc2XXc_interrupt_number
+ * Parameters: const char *module_name
+ * Purpose: Return the module interrupt number
+ * Return Value: unsigned int
+ */
+unsigned int get_spc2XXc_interrupt_number(const char *module_name)
+{
+ unsigned int interrupt_number;
+
+#ifdef CONFIG_UART_FIQ
+ for(interrupt_number=0; interrupt_number<NR_IRQS; interrupt_number++)
+#else
+ for(interrupt_number=0; interrupt_number<64; interrupt_number++)
+#endif
+ {
+ if(!strcmp(module_name, spc2XXc_irq_lines[interrupt_number].name))
+ return interrupt_number;
+ }
+
+ return 0;
+
+} /* get_spc2XXc_interrupt_number */
+
+
+/**
+ * Function: get_spc2XXc_global_mode
+ * Parameters: void
+ * Purpose: Get mode of SPC2XXC
+ * Return Value: int
+ */
+int get_spc2XXc_global_mode(void)
+{
+ return spc2XXc_global_mode;
+}/* get_spc2XXc_global_mode */
+
+/**
+ * Function: get_spc2XXc_FPGA_clock
+ * Parameters: void
+ * Purpose: Get clock of FPGA
+ * Return Value: unsigned int
+ */
+unsigned int get_spc2XXc_FPGA_clock(void)
+{
+ return spc2XXc_FPGA_clock;
+} /* get_spc2XXc_FPGA_clock */
+
+EXPORT_SYMBOL(get_spc2XXc_FPGA_clock);
+EXPORT_SYMBOL(get_spc2XXc_global_mode);
+
+/* Architecture-specific fixups */
+/**
+ * Function: spc2XXc_fixup
+ * Parameters: void
+ * Purpose:
+ * Return Value: void
+ */
+static void __init spc2XXc_fixup(struct machine_desc *desc, struct tag *tags,
+ char **cmdline, struct meminfo *mi)
+{
+ char boot_version[16];
+ char cp_boot_version[16];
+ char *ptr1_boot_version;
+ char *ptr2_boot_version = &cp_boot_version[0];
+
+#ifdef CONFIG_CPU_MXU_ENABLE
+ volatile uint32_t *page_addr;
+ uint32_t base;
+ uint32_t n;
+ register uint32_t zero = 0;
+#endif
+ strncpy(boot_version,(char*)0x08000020,sizeof(boot_version));
+ strncpy(cp_boot_version,boot_version,sizeof(boot_version));
+ ptr1_boot_version = strsep(&ptr2_boot_version, ".");
+
+ if ((simple_strtoul(ptr1_boot_version,NULL,0) >= 2) ||
+ ((simple_strtoul(ptr1_boot_version,NULL,0) == 2) &&
+ (simple_strtoul(ptr2_boot_version,NULL,0) >= 7)))
+ {
+ board_spec_t *board_spec = (void*)BOARD_SPEC_ADDR;
+ SDRAM_size = board_spec->SDRAM_size;
+ }
+
+ DMA_zone_base = SDRAM_BASE+SDRAM_size-DMA_ZONE_SIZE;
+
+ // update tags with SDRAM size
+ for (; tags->hdr.size; tags = tag_next(tags))
+ {
+ if (tags->hdr.tag == ATAG_MEM)
+ {
+ tags->u.mem.size = SDRAM_size;
+ }
+ }
+
+#ifdef CONFIG_CPU_MXU_ENABLE
+ // Turn pages > SDRAM_BASE+SDRAM_size to error
+ base = SDRAM_BASE+SDRAM_size;
+ n = (0x10000000-SDRAM_size)/0x100000;
+
+ while (n)
+ {
+ page_addr = (uint32_t *)(MMU_PAGETABLE_ADDR+(base>>18));
+ *page_addr = 0x0;
+ base += 0x100000;
+ n--;
+ }
+ // Turn pages > DMA_zone_base to uncached
+ base = DMA_zone_base;
+ n = DMA_ZONE_SIZE/0x100000;
+
+ while (n)
+ {
+ page_addr = (uint32_t *)(MMU_PAGETABLE_ADDR+(base>>18));
+ *page_addr = base | 0x00000c12;
+ base += 0x100000;
+ n--;
+ }
+ // flush tlb
+ asm("mcr p15, 0, %0, c8, c7, 0" : : "r" (zero));
+#endif
+} /* spc2XXc_fixup */
+
+/**
+ * Function: spc2XXc_map_io
+ * Parameters: void
+ * Purpose:
+ * Return Value: void
+ */
+#ifdef CONFIG_MMU
+void __init spc2XXc_map_io(void)
+{
+ int serial[SPC2XXC_NR_UART] = SPC2XXC_UART_MAP;
+ int i;
+
+ iotable_init(spc2XXc_periph_internal_desc,
+ ARRAY_SIZE(spc2XXc_periph_internal_desc));
+ iotable_init(spc2XXc_apb_periph_external_desc,
+ ARRAY_SIZE(spc2XXc_apb_periph_external_desc));
+ iotable_init(spc2XXc_ahbeth_periph_external_desc,
+ ARRAY_SIZE(spc2XXc_ahbeth_periph_external_desc));
+ iotable_init(spc2XXc_ahbplc_periph_external_desc,
+ ARRAY_SIZE(spc2XXc_ahbplc_periph_external_desc));
+
+
+ /* Register UARTs */
+ for (i = 0; i < SPC2XXC_NR_UART; i++) {
+ if (serial[i] >= 0)
+ spc2XXc_register_uart(i, serial[i]);
+ }
+} /* spc2XXc_map_io */
+#endif
+
+/**
+ * Function: spc2XXc_ack_irq
+ * Parameters: unsigned int irq
+ * Purpose: Acquit interrupt
+ * Return Value: void
+ */
+void spc2XXc_ack_irq(unsigned int irq)
+{
+ /* Disable interrupt on AIC */
+ if(irq < 32)
+ CSP_GIC_SET_ICCR(CSP_GIC,0,1 << irq);
+} /* spc2XXc_ack_irq */
+
+/**
+ * Function: spc2XXc_mask_irq
+ * Parameters: unsigned int irq
+ * Purpose: Mask interrupt
+ * Return Value: void
+ */
+void spc2XXc_mask_irq(unsigned int irq)
+{
+ /* Disable interrupt on AIC */
+ if(irq < 32)
+ CSP_GIC_SET_IDCR(CSP_GIC,0,1 << irq);
+} /* spc2XXc_mask_irq */
+
+/**
+ * Function: spc2XXc_unmask_irq
+ * Parameters: unsigned int irq
+ * Purpose: Unmask interrupts
+ * Return Value: void
+ */
+void spc2XXc_unmask_irq(unsigned int irq)
+{
+ /* Enable interrupt on AIC */
+ if(irq < 32)
+ CSP_GIC_SET_IECR(CSP_GIC,0,1 << irq);
+} /* spc2XXc_unmask_irq */
+
+
+static struct irqchip spc2XXc_irq_chip = {
+ .ack = spc2XXc_ack_irq,
+ .mask = spc2XXc_mask_irq,
+ .unmask = spc2XXc_unmask_irq,
+}; /* spc2XXc_level_irq_chip */
+
+/**
+ * Function: spc2XXc_init_irq
+ * Parameters: void
+ * Purpose: Initialize SPC2XXC interrupts
+ * Return Value: void
+ */
+void __init spc2XXc_init_irq(void)
+{
+ int irqno;
+
+ /* Disable all interrupts */
+ CSP_GIC_SET_IDCR(CSP_GIC,0,0xFFFFFFFF);
+
+ /* Clear all interrupts */
+ CSP_GIC_SET_ICCR(CSP_GIC,0,0xFFFFFFFF);
+
+ for ( irqno = 0 ; irqno < NR_IRQS ; irqno++ )
+ {
+ CSP_GIC_SET_EOICR(CSP_GIC,irqno);
+ CSP_GIC_SET_SVR(CSP_GIC,irqno,irqno);
+#ifdef CONFIG_UART_FIQ
+ CSP_GIC_SET_SMR(CSP_GIC,irqno,(spc2XXc_irq_lines[irqno].prior
+ | spc2XXc_irq_lines[irqno].sdi
+ | spc2XXc_irq_lines[irqno].type));
+#else
+ CSP_GIC_SET_SMR(CSP_GIC,irqno,(spc2XXc_irq_lines[irqno].prior)
+ | spc2XXc_irq_lines[irqno].type);
+#endif
+ set_irq_chip(irqno,&spc2XXc_irq_chip);
+ set_irq_handler(irqno,do_level_IRQ);
+ set_irq_flags(irqno,IRQF_VALID | IRQF_PROBE);
+ } /* for */
+
+ CSP_GIC_SET_SPU(CSP_GIC, NR_IRQS);
+} /* spc2XXc_init_irq */
+
+int wd_auto_trigger = 1;
+unsigned int wd_trigger_count = 0;
+/**
+ * Function: wd_trigger
+ * Parameters: void
+ * Purpose: watchddog
+ * Return Value: void
+ */
+void wd_trigger(void)
+{
+ wd_trigger_count++;
+ if(CSP_PIO_GET_ODSR((CSP_PIO_PTR)CSP_PIO_BASE) & (1<<1))
+ CSP_PIO_SET_CODR((CSP_PIO_PTR)CSP_PIO_BASE, (unsigned int)(1<<1));
+ else
+ CSP_PIO_SET_SODR((CSP_PIO_PTR)CSP_PIO_BASE, (unsigned int)(1<<1));
+}
+
+/**
+ * Function: spc2XXc_init
+ * Parameters: void
+ * Purpose: Initialize SPC2XXC
+ * Return Value: void
+ */
+static void __init spc2XXc_init(void)
+{
+#if 0
+#if defined (CONFIG_CPU_MXU_ENABLE) && defined(CONFIG_CPU_RO_SRAM)
+ volatile uint32_t *page_addr;
+ uint32_t base;
+ register uint32_t zero = 0;
+#endif
+#endif
+ spc2XXc_init_gpio();
+#ifdef CONFIG_MONA
+ spc2XXc_init_nvram();
+#endif
+#if 0
+#if defined(CONFIG_CPU_MXU_ENABLE) && defined(CONFIG_CPU_RO_SRAM)
+ // Turn SRAM_BASE Read Only
+ base = SRAM_BASE;
+ page_addr = (uint32_t *)(MMU_PAGETABLE_ADDR+(base>>18));
+ // using Domain no 2 (client) for permission check
+ *page_addr = ((uint32_t)base & 0xFFF00000) | 0x0000001e | (0x00000002<<5);
+ // flush tlb
+ asm("mcr p15, 0, %0, c8, c7, 0" : : "r" (zero));
+#endif
+#endif
+} /* spc2XXc_init */
+
+
+MACHINE_START(SPC2XXC, "ARM SPC200c based board")
+ MAINTAINER("SPiDCOM Technologies")
+#ifdef CONFIG_MMU
+ .phys_ram = SDRAM_BASE, // BOOT_MEM(SDRAM_BASE,
+ .phys_io = 0, // 0,
+ .io_pg_offst = (0 >> 18) & 0xfffc, // 0)
+#else
+ .phys_ram = SDRAM_BASE, // BOOT_MEM(SDRAM_BASE,
+ .phys_io = CSP_USART0_BASE, // usart phys addr)
+#endif
+// .param_offset = SDRAM_BASE + 0x100,
+ .fixup = spc2XXc_fixup,
+#ifdef CONFIG_MMU
+ .map_io = spc2XXc_map_io,
+#endif
+ .timer = &spc2XXc_timer,
+ .init_irq = spc2XXc_init_irq,
+ .init_machine = spc2XXc_init,
+MACHINE_END
+
+EXPORT_SYMBOL(SDRAM_size);
+EXPORT_SYMBOL(DMA_zone_base);
+EXPORT_SYMBOL(wd_auto_trigger);
+EXPORT_SYMBOL(wd_trigger);
+EXPORT_SYMBOL(wd_trigger_count);
+
diff --git a/polux/linux-2.6.10/arch/arm/mach-mse500/entry-macro.S b/polux/linux-2.6.10/arch/arm/mach-mse500/entry-macro.S
new file mode 100644
index 0000000000..6c0950b8c0
--- /dev/null
+++ b/polux/linux-2.6.10/arch/arm/mach-mse500/entry-macro.S
@@ -0,0 +1,68 @@
+/******************************************************************************
+* EUROPE TECHNOLOGIES Software Support
+*******************************************************************************
+* The software is delivered "AS IS" without warranty or condition of any
+* kind, either express, implied or statutory. This includes without
+* limitation any warranty or condition with respect to merchantability or
+* fitness for any particular purpose, or against the infringements of
+* intellectual property rights of others.
+*******************************************************************************
+*
+* HISTORY:
+*
+* +----- (NEW | MODify | ADD | DELete)
+* |
+* No# | when who what
+******+***+**********+********************+************************************
+* 000 NEW 22/02/05 ET SW Application Creation
+*******************************************************************************
+*/
+
+#include <asm/hardware.h>
+
+ .macro disable_fiq
+ .endm
+
+/******************
+ * IRQ Workflow !!
+ ******************/
+ .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
+ ldr \base, =(APB_GIC_VA_BA_ASM) @ base virtual address of SYS peripherals
+#ifdef BUG_MULTILAYER
+ ldr \tmp, =(SFM_DUMMY)
+ mov \irqnr, #0
+ str \irqnr,[\tmp]
+#endif /* BUG_MULTILAYER */
+ ldr \irqnr, [\base, #GIC_OFFSET_IVR_ASM] @ read IRQ vector register:de-asserts nIRQ to processor (and clears interrupt)
+ ldr \irqstat, [\base, #GIC_OFFSET_ISR_ASM] @ read interrupt source number
+ teq \irqstat, #0 @ ISR is 0 when no currentinterrupt, or spurious interrupt
+ @streq \tmp, [\base, #GIC_OFFSET_EOICR_ASM] @ not going to be handledfurther, then ACK it now.
+
+ /* WARNING: These lines override the default behaviour, */
+ /* which is to loop back at the start of the macro after the handler */
+
+ /* set r1 to registers address */
+ movne r1, sp
+
+ /* set label 2 as return address */
+ adrsvc ne, lr, 2f
+ .endm
+
+ .macro restore_cpr_and_check_status
+ mov r1, #0
+ ldr r0, =(APB_GIC_VA_BA_ASM)
+#ifdef BUG_MULTILAYER
+ ldr r3, =(SFM_DUMMY)
+ str r1,[r3]
+#endif /* BUG_MULTILAYER */
+ str r1, [r0, #GIC_OFFSET_EOICR_ASM]
+ movs r1, #0
+ .endm
+
+
+ /* This macro is called only for SPC2XXC platform */
+ /* beacuse some processing must be done after the handler */
+ /* and must work under RTAI */
+ .macro irq_prio_table
+ .endm
+
diff --git a/polux/linux-2.6.10/arch/arm/mach-mse500/fiq.S b/polux/linux-2.6.10/arch/arm/mach-mse500/fiq.S
new file mode 100644
index 0000000000..d30f8f9a02
--- /dev/null
+++ b/polux/linux-2.6.10/arch/arm/mach-mse500/fiq.S
@@ -0,0 +1,61 @@
+/*
+ * arch/arm/mach-spc2XXc/fiq.S
+ *
+ * (C) Copyright 2007 Scaleo Chip
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <linux/config.h> /* for CONFIG_ARCH_xxxx */
+#include <linux/linkage.h>
+
+#include <asm/assembler.h>
+#include <asm/constants.h>
+
+
+/*
+ ******************************************************************************
+ * FIQ Entry
+ ******************************************************************************
+ */
+.text
+
+.global spc2XXc_fiq_end
+.global mydata
+
+ENTRY(spc2XXc_fiq_start)
+ /* Adjust and save LR_irq in FIQ stack */
+ sub r14, r14, #4
+ mov r11, pc
+ add r11, r11, #20
+ stmfd r11!, {r14}
+
+
+ /* Mark the End of Interrupt on the GIC */
+ ldr r12, [r9]
+ str r12, [r10]
+
+ /* Restore adjusted LR_irq from FIQ stack directly in the PC */
+ ldmia r11!, {pc}^
+
+mydata_temp:
+ .word 0
+mydata_addr:
+ .word 18
+mydata:
+ .word 0
+spc2XXc_fiq_end:
+
diff --git a/polux/linux-2.6.10/arch/arm/mach-mse500/generic.h b/polux/linux-2.6.10/arch/arm/mach-mse500/generic.h
new file mode 100644
index 0000000000..1c0c85c823
--- /dev/null
+++ b/polux/linux-2.6.10/arch/arm/mach-mse500/generic.h
@@ -0,0 +1,34 @@
+/*
+ * arch/arm/mach-spc2XXc/generic.h
+ *
+ * (C) Copyright 2007 SPiDCOM Technologies
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __GENERIC_H__
+#define __GENERIC_H__
+
+#ifdef CONFIG_MMU
+extern void __init spc2XXc_map_io(void);
+#endif
+extern void __init spc2XXc_init_irq(void);
+extern void spc2XXc_init_gpio(void);
+
+struct sys_timer;
+extern struct sys_timer spc2XXc_timer;
+
+#endif /* __GENERIC_H__ */
diff --git a/polux/linux-2.6.10/arch/arm/mach-mse500/gpio.c b/polux/linux-2.6.10/arch/arm/mach-mse500/gpio.c
new file mode 100644
index 0000000000..60b1abb1c8
--- /dev/null
+++ b/polux/linux-2.6.10/arch/arm/mach-mse500/gpio.c
@@ -0,0 +1,76 @@
+/*
+ * arch/arm/mach-spc2XXc/gpio.c
+ *
+ * (C) Copyright 2007 SPiDCOM Technologies
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <linux/device.h>
+
+#include "platform.h"
+#include "gpio_event.h"
+
+char gpio_map[GPIO_EVENT_MAX];
+
+/**
+ * Function: spc2XXc_init_gpio
+ * Parameters: void
+ * Purpose: Initialize SPC2XXC GPIOs
+ * Return Value: void
+ */
+void spc2XXc_init_gpio(void)
+{
+ //Config GPIOs
+ CSP_PIO_SET_ECR((CSP_PIO_PTR)CSP_PIO_BASE, 0x01); // enable CLK
+ CSP_PIO_SET_PER((CSP_PIO_PTR)CSP_PIO_BASE, 0xFF); // driven by PIO
+ CSP_PIO_SET_MDDR((CSP_PIO_PTR)CSP_PIO_BASE, 0xFF); // not Open Drain
+ CSP_PIO_SET_SODR((CSP_PIO_PTR)CSP_PIO_BASE, (unsigned int)(1<<0)); //put to 1 the software reset
+ CSP_PIO_SET_OER((CSP_PIO_PTR)CSP_PIO_BASE, 0x83); // 0 = RESET (output)
+ // 1 = Watch-Dog (output)
+ // 7 = Plc-System LED (output)
+ CSP_PIO_SET_ODR((CSP_PIO_PTR)CSP_PIO_BASE, 0x7C); // 6 = Safe-return (input)
+ // others are in input
+ CSP_PIO_SET_IDR((CSP_PIO_PTR)CSP_PIO_BASE, 0xFF); // no interrupts
+
+
+ memset(gpio_map, GPIO_NOT_MAPPED, sizeof(gpio_map));
+
+} /* spc2XXc_init_gpio */
+
+
+/**
+ * Function: gpio_write
+ * Parameters: int no and int value
+ * Purpose: write on SPC2XXC GPIOs
+ * Return Value: int
+ */
+int gpio_write(int no, int value)
+{
+ /* GPIO number (no) is from 0 to 7 */
+ if ((no > 7) || (value > 1))
+ return -1;
+
+ if(value)
+ CSP_PIO_SET_SODR((CSP_PIO_PTR)CSP_PIO_BASE, (unsigned int)(1<<no));
+ else
+ CSP_PIO_SET_CODR((CSP_PIO_PTR)CSP_PIO_BASE, (unsigned int)(1<<no));
+
+ return 0;
+}
+
+EXPORT_SYMBOL(gpio_write);
+EXPORT_SYMBOL(gpio_map);
+
diff --git a/polux/linux-2.6.10/arch/arm/mach-mse500/nvram.c b/polux/linux-2.6.10/arch/arm/mach-mse500/nvram.c
new file mode 100644
index 0000000000..498d0a3816
--- /dev/null
+++ b/polux/linux-2.6.10/arch/arm/mach-mse500/nvram.c
@@ -0,0 +1,82 @@
+/*
+ * arch/arm/mach-spc2XXc/nvram.c
+ *
+ * (C) Copyright 2009 SPiDCOM Technologies
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <linux/vmalloc.h>
+#include <linux/proc_fs.h>
+#include <asm/arch/nvram.h>
+
+#ifdef CONFIG_MONA
+int proc_r_nvram (char *buf, char **start, off_t offset, int count, int *eof, void *data)
+{
+ char *p;
+ spidcom_nvram_t nvram, *nvram_ptr;
+ nvram_ptr = &nvram;
+ memcpy(&nvram, (void *)NVRAM_BASE_ADDRESS, sizeof(spidcom_nvram_t));
+
+ p = buf;
+ if(!NVRAM_IS_VALID(nvram_ptr))
+ {
+ p += sprintf(p, "Invalid NVRAM\n");
+ }
+ else
+ {
+ p += sprintf(p, "Serial Number: %s\n", nvram.serialNumber);
+ p += sprintf(p, "System description: %s\n", nvram.sysDescr);
+ p += sprintf(p, "ETH mac address: %02x:%02x:%02x:%02x:%02x:%02x\n",
+ nvram.ethPhysAddress[0], nvram.ethPhysAddress[1], nvram.ethPhysAddress[2],
+ nvram.ethPhysAddress[3], nvram.ethPhysAddress[4], nvram.ethPhysAddress[5]);
+ p += sprintf(p, "PLC mac address: %02x:%02x:%02x:%02x:%02x:%02x\n",
+ nvram.plcPhysAddress[0], nvram.plcPhysAddress[1], nvram.plcPhysAddress[2],
+ nvram.plcPhysAddress[3], nvram.plcPhysAddress[4], nvram.plcPhysAddress[5]);
+ if(NVRAM2_IS_VALID(nvram_ptr))
+ {
+ p += sprintf(p, "Board description: %s\n", nvram.boardDesc);
+ p += sprintf(p, "Board id: %d\n", nvram.boardId);
+ p += sprintf(p, "Vendor info: %s\n", nvram.vendorInfo);
+ p += sprintf(p, "SDRAM size: %d\n", nvram.sdramSize);
+ p += sprintf(p, "Image 0 offset: %08x\n", (unsigned int)nvram.imageOffset0);
+ p += sprintf(p, "Image 1 offset: %08x\n", (unsigned int)nvram.imageOffset1);
+ p += sprintf(p, "Eth port nb: %d\n", nvram.ethPortNum);
+ p += sprintf(p, "Manufactory info: %s\n", nvram.manufactoryInfo);
+ }
+ }
+ *eof = 1;
+ return p - buf + 1;
+}
+#else
+int proc_r_nvram (char *buf, char **start, off_t offset, int count, int *eof, void *data)
+{
+ return buf;
+}
+#endif /* CONFIG_MONA */
+
+
+/**
+ * Function: spc2XXc_init_nvram
+ * Parameters: void
+ * Purpose: Initialize SPC2XXC NVRAM proc info
+ * Return Value: void
+ */
+void spc2XXc_init_nvram(void)
+{
+ create_proc_read_entry ("nvram", 0, NULL, proc_r_nvram, NULL);
+}
+
diff --git a/polux/linux-2.6.10/arch/arm/mach-mse500/time.c b/polux/linux-2.6.10/arch/arm/mach-mse500/time.c
new file mode 100644
index 0000000000..08ef5b1204
--- /dev/null
+++ b/polux/linux-2.6.10/arch/arm/mach-mse500/time.c
@@ -0,0 +1,155 @@
+/*
+ * arch/arm/mach-spc2XXc/time.c
+ *
+ * (C) Copyright 2007 Scaleo Chip
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <linux/config.h>
+#include <linux/kernel.h>
+#include <linux/sched.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/time.h>
+
+#include <asm/hardware.h>
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <asm/mach/time.h>
+#include <asm/system.h>
+#include <asm/arch/system.h>
+
+#define GPIO (CSP_PIO_PTR)CSP_PIO_BASE
+#define GPIO_NUM 0
+
+//#define TIME_COEF (1000000ull)/(TIMER_CLK/PRESCALER)
+#define TIME_COEF (1000*1000)/(TIMER_CLK/PRESCALER)
+
+/**
+ * Function: spc2XXc_gettimeoffset
+ * Parameters: void
+ * Purpose: Returns number of microseconds since last timer interrupt.
+ * Return Value: unsigned long
+ */
+static unsigned long spc2XXc_gettimeoffset(void)
+{
+ unsigned long temp = (CSP_ST16_CHANNEL_GET_CT(CSP_ST0,KERNEL_TIMER) -
+ CSP_ST16_CHANNEL_GET_CCV(CSP_ST0,KERNEL_TIMER)) * TIME_COEF;
+
+ if((CSP_ST16_GET_SR(CSP_ST0) & ST16_CHEND(KERNEL_TIMER)) == ST16_CHEND(KERNEL_TIMER))
+ temp += CSP_ST16_CHANNEL_GET_CT(CSP_ST0,KERNEL_TIMER) * TIME_COEF;
+
+ return temp;
+/* unsigned int time_current;
+// unsigned long temp;
+ unsigned long long lltemp;
+
+ time_current = CSP_ST16_CHANNEL_GET_CCV(CSP_ST0,KERNEL_TIMER);
+ time_current = CSP_ST16_CHANNEL_GET_CCV(CSP_ST0,KERNEL_TIMER);
+
+ lltemp = (CSP_ST16_CHANNEL_GET_CT(CSP_ST0,KERNEL_TIMER) - time_current) * TIME_COEF;
+// lltemp = ((CSP_ST16_CHANNEL_GET_CT(CSP_ST0,KERNEL_TIMER) - time_current) * 1000000ull);
+// lltemp = lltemp / (TIMER_CLK/PRESCALER);
+
+ if((CSP_ST16_GET_SR(CSP_ST0) & ST16_CHEND(KERNEL_TIMER)) == ST16_CHEND(KERNEL_TIMER)) {
+ lltemp += CSP_ST16_CHANNEL_GET_CT(CSP_ST0,KERNEL_TIMER) * TIME_COEF;
+// lltemp += (CSP_ST16_CHANNEL_GET_CT(CSP_ST0,KERNEL_TIMER) * 1000000ull);
+// lltemp = lltemp / (TIMER_CLK/PRESCALER);
+ }
+
+// temp = (unsigned long)lltemp;
+
+ return (unsigned long)lltemp;
+*/
+} /* spc2XXc_gettimeoffset */
+
+extern void wd_trigger(void);
+
+/**
+ * Function: spc2XXc_timer_interrupt
+ * Parameters: int irq, void *dev_id, struct pt_regs *regs
+ * Purpose: IRQ handler for the timer.
+ * Return Value: irqreturn_t
+ */
+static irqreturn_t spc2XXc_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
+{
+// static unsigned char value = 0x01;
+ if(CSP_ST16_GET_SR(CSP_ST0) & ST16_CHEND((KERNEL_TIMER)))
+ {
+ write_seqlock(&xtime_lock);
+ /* If yes, clear it */
+ CSP_ST16_SET_CSR(CSP_ST0,ST16_CHEND((KERNEL_TIMER)));
+ timer_tick(regs);
+ write_sequnlock(&xtime_lock);
+
+ if (wd_auto_trigger)
+ wd_trigger();
+
+ return IRQ_HANDLED;
+ }
+ else
+ return IRQ_NONE; /* not handled */
+} /* spc2XXc_timer_interrupt */
+
+
+static struct irqaction spc2XXc_timer_irq = {
+ .name = "SPC2XXC Timer Tick",
+ .flags = SA_SHIRQ | SA_INTERRUPT,
+ .handler = spc2XXc_timer_interrupt
+}; /* spc2XXc_timer_irq */
+
+/**
+ * Function: spc2XXc_timer_init
+ * Parameters: void
+ * Purpose: Set up timer interrupt.
+ * Return Value: void
+ */
+void __init spc2XXc_timer_init(void)
+{
+ unsigned int int_number;
+
+ /* enable Kernel timer */
+ CSP_ST16_SET_ECR(CSP_ST0, ST16_ST);
+ /* disable interrupt*/
+ CSP_ST16_SET_IDR(CSP_ST0,~0ul);
+ /* disable Simple Timer */
+ CSP_ST16_SET_CR(CSP_ST0,ST16_CHDIS(KERNEL_TIMER));
+ /* reset timer*/
+ CSP_ST16_SET_CR(CSP_ST0,ST16_SWRST);
+ CSP_ST16_SET_CSR(CSP_ST0,ST16_CHEND(KERNEL_TIMER));
+
+ /* Set Prescalar Value CPUCLK/128 + autoreload*/
+ CSP_ST16_CHANNEL_SET_PR(CSP_ST0, KERNEL_TIMER, ST16_AUTOREL | ST16_PRESCAL(PRESCAL_POW));
+
+ /* Configure Counter Value */
+ CSP_ST16_CHANNEL_SET_CT(CSP_ST0, KERNEL_TIMER, ST16_LOAD((TIMER_CLK/PRESCALER)/HZ));
+
+ int_number = get_spc2XXc_interrupt_number("OS Timer");
+ setup_irq(int_number, &spc2XXc_timer_irq);
+
+ CSP_ST16_SET_IER(CSP_ST0,ST16_CHEND(KERNEL_TIMER));
+
+ /* Start channel Timer */
+ CSP_ST16_SET_CR(CSP_ST0,ST16_CHEN(KERNEL_TIMER));
+
+
+} /* spc2XXc_timer_init */
+
+struct sys_timer spc2XXc_timer = {
+ .init = spc2XXc_timer_init,
+ .offset = spc2XXc_gettimeoffset,
+}; /* spc2XXc_timer */
+