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authorCyril Jourdan2012-09-24 17:37:21 +0200
committerCyril Jourdan2012-10-01 13:57:26 +0200
commit64def381dcc7ce19a932792754e48660f4d9fc3d (patch)
treeb78bf9803a996a3e9d154ac534c9cf4a105abd3e /common
parent10a211a8a0ed7f7a18c3107f736c3650518364c2 (diff)
common/inc/asm/arch/ips/hw: add regs phys address for mseafe, refs #3373
Diffstat (limited to 'common')
-rw-r--r--common/include/asm/arch/ips/hardware/mseafe.h47
1 files changed, 47 insertions, 0 deletions
diff --git a/common/include/asm/arch/ips/hardware/mseafe.h b/common/include/asm/arch/ips/hardware/mseafe.h
index a4b32473f2..9a46628f46 100644
--- a/common/include/asm/arch/ips/hardware/mseafe.h
+++ b/common/include/asm/arch/ips/hardware/mseafe.h
@@ -24,6 +24,7 @@
#error "MSEAFE_BASE macro needs to be defined before including file mseafe.h"
#endif
+/* Registers offsets. */
#define MSEAFE_PWR_DOWN_OFFSET (0x00)
#define MSEAFE_AAF_OFFSET (0x04)
#define MSEAFE_AAF_TEST_OFFSET (0x08)
@@ -71,6 +72,52 @@
#define MSEAFE_CAL_PWR_Q_OFFSET (0x104)
#define MSEAFE_MAX_OFFSET MSEAFE_CAL_PWR_Q_OFFSET
+/* Registers physical addresses. */
+#define MSEAFE_PWR_DOWN (MSEAFE_BASE + MSEAFE_PWR_DOWN_OFFSET)
+#define MSEAFE_AAF (MSEAFE_BASE + MSEAFE_AAF_OFFSET)
+#define MSEAFE_AAF_TEST (MSEAFE_BASE + MSEAFE_AAF_TEST_OFFSET)
+#define MSEAFE_LNA (MSEAFE_BASE + MSEAFE_LNA_OFFSET)
+#define MSEAFE_LNA_TEST (MSEAFE_BASE + MSEAFE_LNA_TEST_OFFSET)
+#define MSEAFE_REF_TEST (MSEAFE_BASE + MSEAFE_REF_TEST_OFFSET)
+#define MSEAFE_IO (MSEAFE_BASE + MSEAFE_IO_OFFSET)
+#define MSEAFE_ATOP_TEST_LOW (MSEAFE_BASE + MSEAFE_ATOP_TEST_LOW_OFFSET)
+#define MSEAFE_ATOP_TEST_HIGH (MSEAFE_BASE + MSEAFE_ATOP_TEST_HIGH_OFFSET)
+#define MSEAFE_ADC_TEST (MSEAFE_BASE + MSEAFE_ADC_TEST_OFFSET)
+#define MSEAFE_VOLT_CTRL (MSEAFE_BASE + MSEAFE_VOLT_CTRL_OFFSET)
+#define MSEAFE_ADC_CFG (MSEAFE_BASE + MSEAFE_ADC_CFG_OFFSET)
+#define MSEAFE_DAC_INPUT (MSEAFE_BASE + MSEAFE_DAC_INPUT_OFFSET)
+#define MSEAFE_DAC_CFG (MSEAFE_BASE + MSEAFE_DAC_CFG_OFFSET)
+#define MSEAFE_DAC_LEV_REG (MSEAFE_BASE + MSEAFE_DAC_LEV_REG_OFFSET)
+#define MSEAFE_XTAL_PWD_LOW (MSEAFE_BASE + MSEAFE_XTAL_PWD_LOW_OFFSET)
+#define MSEAFE_XTAL_PWD_HIGH (MSEAFE_BASE + MSEAFE_XTAL_PWD_HIGH_OFFSET)
+#define MSEAFE_GEN_CFG_1 (MSEAFE_BASE + MSEAFE_GEN_CFG_1_OFFSET)
+#define MSEAFE_CALIB_1 (MSEAFE_BASE + MSEAFE_CALIB_1_OFFSET)
+#define MSEAFE_CALIB_2 (MSEAFE_BASE + MSEAFE_CALIB_2_OFFSET)
+#define MSEAFE_CALIB_3 (MSEAFE_BASE + MSEAFE_CALIB_3_OFFSET)
+#define MSEAFE_GEN_CFG_2 (MSEAFE_BASE + MSEAFE_GEN_CFG_2_OFFSET)
+#define MSEAFE_DELAY_1 (MSEAFE_BASE + MSEAFE_DELAY_1_OFFSET)
+#define MSEAFE_DELAY_2 (MSEAFE_BASE + MSEAFE_DELAY_2_OFFSET)
+#define MSEAFE_GEN_CFG_3 (MSEAFE_BASE + MSEAFE_GEN_CFG_3_OFFSET)
+#define MSEAFE_PAT_STEP (MSEAFE_BASE + MSEAFE_PAT_STEP_OFFSET)
+#define MSEAFE_NCO1_FREQ (MSEAFE_BASE + MSEAFE_NCO1_FREQ_OFFSET)
+#define MSEAFE_NCO2_FREQ (MSEAFE_BASE + MSEAFE_NCO2_FREQ_OFFSET)
+#define MSEAFE_TONES_GAIN (MSEAFE_BASE + MSEAFE_TONES_GAIN_OFFSET)
+#define MSEAFE_NCO1_PHASE (MSEAFE_BASE + MSEAFE_NCO1_PHASE_OFFSET)
+#define MSEAFE_GEN_CFG_4 (MSEAFE_BASE + MSEAFE_GEN_CFG_4_OFFSET)
+#define MSEAFE_RX_DCC (MSEAFE_BASE + MSEAFE_RX_DCC_OFFSET)
+#define MSEAFE_RESERVED (MSEAFE_BASE + MSEAFE_RESERVED_OFFSET)
+#define MSEAFE_DPLL_CTRL (MSEAFE_BASE + MSEAFE_DPLL_CTRL_OFFSET)
+#define MSEAFE_DPLL_LOOP_DIV (MSEAFE_BASE + MSEAFE_DPLL_LOOP_DIV_OFFSET)
+#define MSEAFE_DPLL_TEST_LOW (MSEAFE_BASE + MSEAFE_DPLL_TEST_LOW_OFFSET)
+#define MSEAFE_DPLL_TEST_HIGH (MSEAFE_BASE + MSEAFE_DPLL_TEST_HIGH_OFFSET)
+#define MSEAFE_DPLL_CONF (MSEAFE_BASE + MSEAFE_DPLL_CONF_OFFSET)
+#define MSEAFE_AFE_TEST_CFG (MSEAFE_BASE + MSEAFE_AFE_TEST_CFG_OFFSET)
+#define MSEAFE_AFE_DEBUG_OUT_LOW (MSEAFE_BASE + MSEAFE_AFE_DEBUG_OUT_LOW_OFFSET)
+#define MSEAFE_AFE_DEBUG_OUT_HIGH (MSEAFE_BASE + MSEAFE_AFE_DEBUG_OUT_HIGH_OFFSET)
+#define MSEAFE_AFE_TEST_OUT (MSEAFE_BASE + MSEAFE_AFE_TEST_OUT_OFFSET)
+#define MSEAFE_AFE_SOFT_RST (MSEAFE_BASE + MSEAFE_AFE_SOFT_RST_OFFSET)
+#define MSEAFE_CAL_PWR_I (MSEAFE_BASE + MSEAFE_CAL_PWR_I_OFFSET)
+#define MSEAFE_CAL_PWR_Q (MSEAFE_BASE + MSEAFE_CAL_PWR_Q_OFFSET)
/** Bitfields for DPLL CTRL. */
#define MSEAFE_DPLL_CTRL_PD_CLK_SHIFT 0