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authorJean-Philippe SAVE2012-08-31 14:27:10 +0200
committerCyril Jourdan2012-09-20 16:56:24 +0200
commita943be7d78b7de5604bedbdede4cc1e7207a98be (patch)
treebacd66bc6de32ed234bcc77f05add268b2546d9e /common/include/asm
parentb3e493a8603c4a4d7c8420724fd7b6802af84a36 (diff)
common/inc/asm/arch/ips/hw: add mseafe.h, refs #3318
Diffstat (limited to 'common/include/asm')
-rw-r--r--common/include/asm/arch/ips/hardware/bus_sys.h5
-rw-r--r--common/include/asm/arch/ips/hardware/mseafe.h139
2 files changed, 144 insertions, 0 deletions
diff --git a/common/include/asm/arch/ips/hardware/bus_sys.h b/common/include/asm/arch/ips/hardware/bus_sys.h
index 7a9d44e1cb..53541c4370 100644
--- a/common/include/asm/arch/ips/hardware/bus_sys.h
+++ b/common/include/asm/arch/ips/hardware/bus_sys.h
@@ -57,6 +57,11 @@
#define DSP_BASE (0xA0000000)
#include "dsp.h"
+#if defined (CONFIG_AFE_MSEAFE)
+#define MSEAFE_BASE (0xEC003800)
+#include "mseafe.h"
+#endif
+
#if defined (CONFIG_CHIP_FEATURE_MSEPLL)
#define MSEPLL_SPLL_BASE (0xEC000400)
#define MSEPLL_PPLL_BASE (0xEC000600)
diff --git a/common/include/asm/arch/ips/hardware/mseafe.h b/common/include/asm/arch/ips/hardware/mseafe.h
new file mode 100644
index 0000000000..1b3123de69
--- /dev/null
+++ b/common/include/asm/arch/ips/hardware/mseafe.h
@@ -0,0 +1,139 @@
+/*
+ * include/asm/arch/ips/hardware/mseafe.h
+ *
+ * Copyright (C) 2012 MStar Semiconductor.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software Foundation,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+#ifndef __ASM_ARCH_IPS_HW_MSEAFE_H
+#define __ASM_ARCH_IPS_HW_MSEAFE_H
+
+#ifndef MSEAFE_BASE
+ #error "MSEAFE_BASE macro needs to be defined before including file mseafe.h"
+#endif
+
+#define MSEAFE_PWR_DOWN_OFFSET (0x00)
+#define MSEAFE_AAF_OFFSET (0x04)
+#define MSEAFE_AAF_TEST_OFFSET (0x08)
+#define MSEAFE_LNA_OFFSET (0x0c)
+#define MSEAFE_LNA_TEST_OFFSET (0x10)
+#define MSEAFE_REF_TEST_OFFSET (0x14)
+#define MSEAFE_IO_OFFSET (0x18)
+#define MSEAFE_ATOP_TEST_LOW_OFFSET (0x1c)
+#define MSEAFE_ATOP_TEST_HIGH_OFFSET (0x20)
+#define MSEAFE_ADC_TEST_OFFSET (0x24)
+#define MSEAFE_VOLT_CTRL_OFFSET (0x28)
+#define MSEAFE_ADC_CFG_OFFSET (0x2c)
+#define MSEAFE_DAC_INPUT_OFFSET (0x30)
+#define MSEAFE_DAC_CFG_OFFSET (0x34)
+#define MSEAFE_DAC_LEV_REG_OFFSET (0x38)
+#define MSEAFE_XTAL_PWD_LOW_OFFSET (0x40)
+#define MSEAFE_XTAL_PWD_HIGH_OFFSET (0x44)
+#define MSEAFE_GEN_CFG_1_OFFSET (0x80)
+#define MSEAFE_CALIB_1_OFFSET (0x84)
+#define MSEAFE_CALIB_2_OFFSET (0x88)
+#define MSEAFE_CALIB_3_OFFSET (0x8c)
+#define MSEAFE_GEN_CFG_2_OFFSET (0x90)
+#define MSEAFE_DELAY_1_OFFSET (0x94)
+#define MSEAFE_DELAY_2_OFFSET (0x98)
+#define MSEAFE_GEN_CFG_3_OFFSET (0x9c)
+#define MSEAFE_PAT_STEP_OFFSET (0xa0)
+#define MSEAFE_NCO1_FREQ_OFFSET (0xa4)
+#define MSEAFE_NCO2_FREQ_OFFSET (0xa8)
+#define MSEAFE_TONES_GAIN_OFFSET (0xac)
+#define MSEAFE_NCO1_PHASE_OFFSET (0xb0)
+#define MSEAFE_GEN_CFG_4_OFFSET (0xb4)
+#define MSEAFE_RX_DCC_OFFSET (0xb8)
+#define MSEAFE_RESERVED_OFFSET (0xbc)
+#define MSEAFE_DPLL_CTRL_OFFSET (0xc0)
+#define MSEAFE_DPLL_LOOP_DIV_OFFSET (0xc4)
+#define MSEAFE_DPLL_TEST_LOW_OFFSET (0xcc)
+#define MSEAFE_DPLL_TEST_HIGH_OFFSET (0xd0)
+#define MSEAFE_DPLL_CONF_OFFSET (0xd4)
+#define MSEAFE_AFE_TEST_CFG_OFFSET (0xdc)
+#define MSEAFE_AFE_DEBUG_OUT_LOW_OFFSET (0xe0)
+#define MSEAFE_AFE_DEBUG_OUT_HIGH_OFFSET (0xe4)
+#define MSEAFE_AFE_TEST_OUT_OFFSET (0xe8)
+#define MSEAFE_AFE_SOFT_RST_OFFSET (0xfc)
+#define MSEAFE_CAL_PWR_I_OFFSET (0x100)
+#define MSEAFE_CAL_PWR_Q_OFFSET (0x104)
+
+
+/** Bitfields for DPLL CTRL. */
+#define MSEAFE_DPLL_CTRL_PD_CLK_SHIFT 0
+#define MSEAFE_DPLL_CTRL_PD_CLK_MASK 0x1
+#define MSEAFE_DPLL_CTRL_PD_3V3_SHIFT 1
+#define MSEAFE_DPLL_CTRL_PD_3V3_MASK 0x1F
+#define MSEAFE_DPLL_CTRL_PD_DAC_CLK_OUT_SHIFT 7
+#define MSEAFE_DPLL_CTRL_PD_DAC_CLK_OUT_MASK 0x1
+#define MSEAFE_DPLL_CTRL_ADC_DIV_SHIFT 8
+#define MSEAFE_DPLL_CTRL_ADC_DIV_MASK 0x7
+#define MSEAFE_DPLL_CTRL_REF_DIV_SHIFT 12
+#define MSEAFE_DPLL_CTRL_REF_DIV_MASK 0x3
+#define MSEAFE_DPLL_CTRL_PD_DAC_CLK_SHIFT 14
+#define MSEAFE_DPLL_CTRL_PD_DAC_CLK_MASK 0x1
+#define MSEAFE_DPLL_CTRL_PD_ADC_CLK_SHIFT 15
+#define MSEAFE_DPLL_CTRL_PD_ADC_CLK_MASK 0x1
+
+/** Values for DPLL CTRL. */
+#define MSEAFE_DPLL_CTRL_ADC_DIV_2 0
+#define MSEAFE_DPLL_CTRL_ADC_DIV_3 1
+#define MSEAFE_DPLL_CTRL_ADC_DIV_4 2
+#define MSEAFE_DPLL_CTRL_ADC_DIV_6 4
+#define MSEAFE_DPLL_CTRL_ADC_DIV_16 5
+#define MSEAFE_DPLL_CTRL_REF_DIV_1 0
+#define MSEAFE_DPLL_CTRL_REF_DIV_2 1
+
+/** Bitfields for DPLL LOOP_DIV. */
+#define MSEAFE_DPLL_LOOP_DIV_FIRST_SHIFT 0
+#define MSEAFE_DPLL_LOOP_DIV_FIRST_MASK 0x3
+#define MSEAFE_DPLL_LOOP_DIV_SECOND_SHIFT 8
+#define MSEAFE_DPLL_LOOP_DIV_SECOND_MASK 0xFF
+
+/** Values for DPLL LOOP_DIV. */
+#define MSEAFE_DPLL_LOOP_DIV_FIRST_1 0
+#define MSEAFE_DPLL_LOOP_DIV_FIRST_2 1
+
+/** Bitfields for DPLL CONF. */
+#define MSEAFE_DPLL_CONF_ICP_SHIFT 0
+#define MSEAFE_DPLL_CONF_ICP_MASK 0x7
+#define MSEAFE_DPLL_CONF_IN_SEL_SHIFT 3
+#define MSEAFE_DPLL_CONF_IN_SEL_MASK 0x1
+#define MSEAFE_DPLL_CONF_XTAL2ADC_SEL_SHIFT 4
+#define MSEAFE_DPLL_CONF_XTAL2ADC_SEL_MASK 0x1
+#define MSEAFE_DPLL_CONF_PD_SHIFT 7
+#define MSEAFE_DPLL_CONF_PD_MASK 0x1
+#define MSEAFE_DPLL_CONF_DAC_DIV_SHIFT 8
+#define MSEAFE_DPLL_CONF_DAC_DIV_MASK 0x7
+#define MSEAFE_DPLL_CONF_DSP_DIV_SHIFT 12
+#define MSEAFE_DPLL_CONF_DSP_DIV_MASK 0x7
+
+/** Values for DPLL CONF. */
+#define MSEAFE_DPLL_CONF_IN_SEL_3V3 0
+#define MSEAFE_DPLL_CONF_IN_SEL_1V2 1
+#define MSEAFE_DPLL_CONF_DAC_DIV_2 0
+#define MSEAFE_DPLL_CONF_DAC_DIV_3 1
+#define MSEAFE_DPLL_CONF_DAC_DIV_4 2
+#define MSEAFE_DPLL_CONF_DAC_DIV_6 4
+#define MSEAFE_DPLL_CONF_DSP_DIV_2 0
+#define MSEAFE_DPLL_CONF_DSP_DIV_3 1
+#define MSEAFE_DPLL_CONF_DSP_DIV_4 2
+#define MSEAFE_DPLL_CONF_DSP_DIV_6 4
+
+/** Globals defines for enable and disable registers. */
+#define MSEAFE_CMD_OFF 0
+#define MSEAFE_CMD_ON 1
+
+#endif /* __ASM_ARCH_IPS_HW_MSEAFE_H */