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authorBelkadi & Save2011-07-13 16:31:28 +0200
committerBelkadi & Save2011-07-13 16:31:28 +0200
commita3dab39f3157a8ff28b74e934d164aa4e3ebf3e2 (patch)
tree6f630b26f3a479af89cfe8ee51cbaa2ad5285ab4 /cleopatre
parentb192aa5b757db30843ef70da76c1fce331e0919c (diff)
cleo/u-boot: move sdram controller config into its own file
Diffstat (limited to 'cleopatre')
-rw-r--r--cleopatre/u-boot-1.1.6/cpu/spc300/Makefile2
-rw-r--r--cleopatre/u-boot-1.1.6/cpu/spc300/sdram.S89
-rw-r--r--cleopatre/u-boot-1.1.6/cpu/spc300/start.S56
3 files changed, 93 insertions, 54 deletions
diff --git a/cleopatre/u-boot-1.1.6/cpu/spc300/Makefile b/cleopatre/u-boot-1.1.6/cpu/spc300/Makefile
index cb4bf1243c..6c4ccc9b1f 100644
--- a/cleopatre/u-boot-1.1.6/cpu/spc300/Makefile
+++ b/cleopatre/u-boot-1.1.6/cpu/spc300/Makefile
@@ -23,7 +23,7 @@ LIB = lib$(CPU).a
START = start.o
OBJS = interrupts.o cpu.o timer.o serial.o wdt.o
-SOBJS = reset.o pll_init.o eth_init.o nvram.o dsp.o
+SOBJS = reset.o pll_init.o eth_init.o nvram.o dsp.o sdram.o
all: .depend $(START) $(LIB)
diff --git a/cleopatre/u-boot-1.1.6/cpu/spc300/sdram.S b/cleopatre/u-boot-1.1.6/cpu/spc300/sdram.S
new file mode 100644
index 0000000000..364cfde74a
--- /dev/null
+++ b/cleopatre/u-boot-1.1.6/cpu/spc300/sdram.S
@@ -0,0 +1,89 @@
+/*
+ * cpu/spc300/sdram.S
+ *
+ * Copyright (C) 2011 SPiDCOM Technologies
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <asm/arch/nvram.h>
+
+ .file "sdram.S"
+
+ .text
+ .arm @ This is ARM code; performs the same action as .code 32
+ .align 2 @ Align to word boundary; "2" means the number of bits that must be zero
+ .globl sdram_init
+ .type sdram_init, %function
+
+
+sdram_init:
+ /* set up return latency, needed for system clock */
+ ldr r0, =REGBANK_BASE
+ mov r1, #0
+ str r1, [r0, #RB_SDRAM_RETURN_LAT]
+
+ /* do sdram init */
+ ldr r1, =SDRAM_CTRL_BASE
+
+ /* SCONR */
+ ldr r2, [r10, #NVRAM_SDRAM_CONFIG_OFFSET] /* load SCONR content from NVRAM */
+ str r2, [r1, #SCONR] /* store configuration to config reg */
+
+ /* STMG0R */
+ ldr r2, [r10, #NVRAM_SDRAM_TIMING0_OFFSET] /* load STMG0R content from NVRAM */
+ str r2, [r1, #STMG0R] /* store configuration to config reg */
+
+ /* STMG1R */
+ ldr r2, [r10, #NVRAM_SDRAM_TIMING1_OFFSET] /* load STMG1R content from NVRAM */
+ str r2, [r1, #STMG1R] /* store configuration to config reg */
+
+ /* SREFR */
+ ldr r2, [r10, #NVRAM_SDRAM_REFRESH_OFFSET] /* load SREFR content from NVRAM */
+ str r2, [r1, #SREFR] /* store configuration to config reg */
+
+ /* Find Freq parameters from NVRAM (struct address is in r10) */
+ ldr r2, [r10, #NVRAM_PKG_CFG_OFFSET] /* load pkg_cfg */
+ lsr r2, r2, #NVRAM_FREQ_SHIFT
+ and r2, r2, #NVRAM_FREQ_MASK /* r2 = freq */
+ cmp r2, #NVRAM_FREQ_150 /* freq = 150MHz ? */
+ bne .NotHighSpeed /* no : don't touch pipe and latch */
+
+ /* Increase Read Pipe when freq > 143MHz */
+ ldr r2, [r1, #SCTLR] /* r2 = SCTLR */
+ orr r2, r2, #(0x03 << SCTLR_read_pipe_BitAddressOffset)
+ str r2, [r1, #SCTLR] /* SCTLR -> set read pipe to 3 */
+
+ /* Set SDRAM latch when freq > 143MHZ */
+ ldr r3, =MARIA_REGBANK_BASE
+ mov r2, #1
+ str r2, [r3, #RB_SDRAM_RETURN_LAT]
+
+.NotHighSpeed:
+ /* reinitialize SDRAM for changes to take effect */
+ ldr r2, [r1, #SCTLR] /* r2 = SCTLR */
+ orr r2, r2, #0x01
+ str r2, [r1, #SCTLR] /* SCTLR -> initialize sdram */
+.Lsdramreset:
+ ldr r0, =SDRAM_CTRL_BASE
+ ldr r1, [r0, #SCTLR]
+ and r1, r1, #0x01
+ cmp r1, #0
+ bne .Lsdramreset
+
+ /* Back to my caller. */
+ mov pc, lr
diff --git a/cleopatre/u-boot-1.1.6/cpu/spc300/start.S b/cleopatre/u-boot-1.1.6/cpu/spc300/start.S
index fdaa7d5fd9..9ca66207a9 100644
--- a/cleopatre/u-boot-1.1.6/cpu/spc300/start.S
+++ b/cleopatre/u-boot-1.1.6/cpu/spc300/start.S
@@ -379,59 +379,9 @@ poll_RB_CLK_DIV_STAT_ARM:
/*
* SDRAM and board specific bits setup prior to relocation.
*/
- /* set up return latency, needed for system clock */
- ldr r0, =REGBANK_BASE
- mov r1, #0
- str r1, [r0, #RB_SDRAM_RETURN_LAT]
-
- /* do sdram init */
- ldr r1, =SDRAM_CTRL_BASE
-
- /* SCONR */
- ldr r2, [r10, #NVRAM_SDRAM_CONFIG_OFFSET] /* load SCONR content from NVRAM */
- str r2, [r1, #SCONR] /* store configuration to config reg */
-
- /* STMG0R */
- ldr r2, [r10, #NVRAM_SDRAM_TIMING0_OFFSET] /* load STMG0R content from NVRAM */
- str r2, [r1, #STMG0R] /* store configuration to config reg */
-
- /* STMG1R */
- ldr r2, [r10, #NVRAM_SDRAM_TIMING1_OFFSET] /* load STMG1R content from NVRAM */
- str r2, [r1, #STMG1R] /* store configuration to config reg */
-
- /* SREFR */
- ldr r2, [r10, #NVRAM_SDRAM_REFRESH_OFFSET] /* load SREFR content from NVRAM */
- str r2, [r1, #SREFR] /* store configuration to config reg */
-
- /* Find Freq parameters from NVRAM (struct address is in r10) */
- ldr r2, [r10, #NVRAM_PKG_CFG_OFFSET] /* load pkg_cfg */
- lsr r2, r2, #NVRAM_FREQ_SHIFT
- and r2, r2, #NVRAM_FREQ_MASK /* r2 = freq */
- cmp r2, #NVRAM_FREQ_150 /* freq = 150MHz ? */
- bne .NotHighSpeed /* no : don't touch pipe and latch */
-
- /* Increase Read Pipe when freq > 143MHz */
- ldr r2, [r1, #SCTLR] /* r2 = SCTLR */
- orr r2, r2, #(0x03 << SCTLR_read_pipe_BitAddressOffset)
- str r2, [r1, #SCTLR] /* SCTLR -> set read pipe to 3 */
-
- /* Set SDRAM latch when freq > 143MHZ */
- ldr r3, =MARIA_REGBANK_BASE
- mov r2, #1
- str r2, [r3, #RB_SDRAM_RETURN_LAT]
-
-.NotHighSpeed:
- /* reinitialize SDRAM for changes to take effect */
- ldr r2, [r1, #SCTLR] /* r2 = SCTLR */
- orr r2, r2, #0x01
- str r2, [r1, #SCTLR] /* SCTLR -> initialize sdram */
-.Lsdramreset:
- ldr r0, =SDRAM_CTRL_BASE
- ldr r1, [r0, #SCTLR]
- and r1, r1, #0x01
- cmp r1, #0
- bne .Lsdramreset
-
+ mov ip, lr /* perserve link reg across call */
+ bl sdram_init /* we pass NVRAM addr in r10; do not corrupt r10 in this function */
+ mov lr, ip /* restore link */
/*
* All vital periphs configured, exit cpu_init_crit