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authorsave2009-01-14 10:03:57 +0000
committersave2009-01-14 10:03:57 +0000
commita2976f4ae7c106f0cd9442d8c50446afd5720266 (patch)
tree0dff4c469481151f856f15396d3752242f8db4e7 /cleopatre
parent6d719f4767618a4b4507b8f4b7013d4180bb565b (diff)
[CLEO][KERNEL]Oups forgot one new Hardware define file
git-svn-id: svn+ssh://pessac/svn/cesar/trunk@3760 017c9cb6-072f-447c-8318-d5b54f68fe89
Diffstat (limited to 'cleopatre')
-rw-r--r--cleopatre/linux-2.6.25.10/include/asm-arm/arch-spc300/hardware/pkg_maria_regbank.h214
1 files changed, 214 insertions, 0 deletions
diff --git a/cleopatre/linux-2.6.25.10/include/asm-arm/arch-spc300/hardware/pkg_maria_regbank.h b/cleopatre/linux-2.6.25.10/include/asm-arm/arch-spc300/hardware/pkg_maria_regbank.h
new file mode 100644
index 0000000000..dd24b5dca6
--- /dev/null
+++ b/cleopatre/linux-2.6.25.10/include/asm-arm/arch-spc300/hardware/pkg_maria_regbank.h
@@ -0,0 +1,214 @@
+#ifndef __ASM_ARCH_PKG_MARIA_REGBANK_H
+#define __ASM_ARCH_PKG_MARIA_REGBANK_H
+
+#ifndef MARIA_REGBANK_BASE
+ #error "MARIA_REGBANK_BASE macro needs to be defined before including file pkg_maria_regbank.h"
+#endif
+
+
+#define TRUE (0x1)
+#define SLAVE_MARIA_REGBANK (0x8030)
+#define RB_PACKAGE (MARIA_REGBANK_BASE+0x000)
+#define PACKAGE_PFBGA265 (0x0)
+#define PACKAGE_LQFP176 (0x1)
+#define RB_SDRAM_RETURN_LAT (MARIA_REGBANK_BASE+0x004)
+#define RB_MARIA_IMPLEMENTATION (MARIA_REGBANK_BASE+0x008)
+#define MARIA_IMPLEMENTATION_ASIC (0x0)
+#define MARIA_IMPLEMENTATION_FCM3 (0x1)
+#define RB_BUS_SYS_REMAPPED (MARIA_REGBANK_BASE+0x100)
+#define RB_BUS_SYS_ARBITER_INIT (MARIA_REGBANK_BASE+0x104)
+#define RB_BUS_SYS_ARBITER_INIT_VALUE (MARIA_REGBANK_BASE+0x108)
+#define RB_BUS_INTF_ARBITER_INIT (MARIA_REGBANK_BASE+0x10c)
+#define RB_BUS_INTF_ARBITER_INIT_VALUE (MARIA_REGBANK_BASE+0x110)
+#define RB_BUS_DSP_ARBITER_INIT (MARIA_REGBANK_BASE+0x114)
+#define RB_BUS_DSP_ARBITER_INIT_VALUE (MARIA_REGBANK_BASE+0x118)
+#define RB_ICM_PRIORITY (MARIA_REGBANK_BASE+0x11c)
+#define RB_LEON_ADD_START (MARIA_REGBANK_BASE+0x120)
+#define RB_LEON_TICK_CNT (MARIA_REGBANK_BASE+0x124)
+#define LEON_ADD_START_RESET (0x00011000)
+#define LEON_TICK_CNT_RESET (0x1d4c)
+#define RB_PIO_CONFIG (MARIA_REGBANK_BASE+0x200)
+#define PIO_CONFIG_0 (0x0)
+#define PIO_CONFIG_1 (0x1)
+#define PIO_CONFIG_2 (0x2)
+#define PIO_CONFIG_3 (0x3)
+#define PIO_CONFIG_4 (0x4)
+#define PIO_CONFIG_5 (0x5)
+#define PIO_CONFIG_6 (0x6)
+#define PIO_CONFIG_7 (0x7)
+#define RB_PIO_ENABLE (MARIA_REGBANK_BASE+0x204)
+#define RB_GPIO_0_CONFIG (MARIA_REGBANK_BASE+0x208)
+#define RB_GPIO_1_CONFIG (MARIA_REGBANK_BASE+0x20c)
+#define RB_GPIO_2_CONFIG (MARIA_REGBANK_BASE+0x210)
+#define RB_GPIO_3_CONFIG (MARIA_REGBANK_BASE+0x214)
+#define RB_GPIO_4_CONFIG (MARIA_REGBANK_BASE+0x218)
+#define RB_GPIO_5_CONFIG (MARIA_REGBANK_BASE+0x21c)
+#define RB_GPIO_6_CONFIG (MARIA_REGBANK_BASE+0x220)
+#define RB_GPIO_7_CONFIG (MARIA_REGBANK_BASE+0x224)
+#define RB_GPIO_8_CONFIG (MARIA_REGBANK_BASE+0x228)
+#define RB_GPIO_9_CONFIG (MARIA_REGBANK_BASE+0x22c)
+#define RB_GPIO_10_CONFIG (MARIA_REGBANK_BASE+0x230)
+#define RB_GPIO_11_CONFIG (MARIA_REGBANK_BASE+0x234)
+#define RB_GPIO_12_CONFIG (MARIA_REGBANK_BASE+0x238)
+#define RB_GPIO_13_CONFIG (MARIA_REGBANK_BASE+0x23c)
+#define RB_GPIO_14_CONFIG (MARIA_REGBANK_BASE+0x240)
+#define RB_GPIO_15_CONFIG (MARIA_REGBANK_BASE+0x244)
+#define RB_GPIO_DEBUG (MARIA_REGBANK_BASE+0x248)
+#define GPIO_CONFIG_0 (0x0)
+#define GPIO_CONFIG_1 (0x1)
+#define GPIO_CONFIG_2 (0x2)
+#define GPIO_CONFIG_3 (0x3)
+#define GPIO_CONFIG_4 (0x4)
+#define GPIO_CONFIG_5 (0x5)
+#define GPIO_CONFIG_6 (0x6)
+#define GPIO_CONFIG_7 (0x7)
+#define GPIO_CONFIG_8 (0x8)
+#define GPIO_CONFIG_9 (0x9)
+#define RB_WDT_SPEED_UP (MARIA_REGBANK_BASE+0x300)
+#define RB_AFE_CLKO_POL (MARIA_REGBANK_BASE+0x304)
+#define CLK_CMD_ON (0x1)
+#define CLK_CMD_OFF (0x0)
+#define CLK_IS_ON (0x1)
+#define CLK_IS_OFF (0x2)
+#define CLK_CMD_BYPASS (0x1)
+#define CLK_CMD_PLL (0x0)
+#define CLK_IS_BYPASS (0x1)
+#define CLK_IS_PLL (0x2)
+#define RB_CLK_CMD_ETH_RMII (MARIA_REGBANK_BASE+0x400)
+#define RB_CLK_STAT_ETH_RMII (MARIA_REGBANK_BASE+0x404)
+#define RB_CLK_DIV_ETH_25 (MARIA_REGBANK_BASE+0x408)
+#define RB_CLK_DIV_STAT_ETH_25 (MARIA_REGBANK_BASE+0x40C)
+#define CLK_DIV_ETH_25_2 (0x0)
+#define CLK_DIV_ETH_25_20 (0x1)
+#define RB_CLK_CMD_ETH_TX_EXT (MARIA_REGBANK_BASE+0x410)
+#define RB_CLK_STAT_ETH_TX_EXT (MARIA_REGBANK_BASE+0x414)
+#define RB_CLK_CMD_ETH_TX_125 (MARIA_REGBANK_BASE+0x420)
+#define RB_CLK_STAT_ETH_TX_125 (MARIA_REGBANK_BASE+0x424)
+#define RB_CLK_SEL_ETH_TX (MARIA_REGBANK_BASE+0x430)
+#define RB_CLK_SEL_STAT_ETH_TX (MARIA_REGBANK_BASE+0x434)
+#define CLK_SEL_ETH_TX_25 (0x0)
+#define CLK_SEL_ETH_TX_125 (0x1)
+#define CLK_SEL_ETH_TX_EXT (0x2)
+#define RB_CLK_CMD_ETH_RX_EXT (MARIA_REGBANK_BASE+0x440)
+#define RB_CLK_STAT_ETH_RX_EXT (MARIA_REGBANK_BASE+0x444)
+#define RB_CLK_SEL_ETH_RX (MARIA_REGBANK_BASE+0x450)
+#define RB_CLK_SEL_STAT_ETH_RX (MARIA_REGBANK_BASE+0x454)
+#define CLK_SEL_ETH_RX_25 (0x0)
+#define CLK_SEL_ETH_RX_EXT (0x1)
+#define RB_CLK_SEL_ETH_MAC (MARIA_REGBANK_BASE+0x460)
+#define RB_CLK_SEL_STAT_ETH_MAC (MARIA_REGBANK_BASE+0x464)
+#define CLK_SEL_ETH_MAC_RMII (0x0)
+#define CLK_SEL_ETH_MAC_125 (0x1)
+#define RB_CLK_CMD_DSP (MARIA_REGBANK_BASE+0x470)
+#define RB_CLK_STAT_DSP (MARIA_REGBANK_BASE+0x474)
+#define RB_CLK_CMD_AFE (MARIA_REGBANK_BASE+0x480)
+#define RB_CLK_STAT_AFE (MARIA_REGBANK_BASE+0x484)
+#define RB_CLK_CMD_ARM (MARIA_REGBANK_BASE+0x490)
+#define RB_CLK_STAT_ARM (MARIA_REGBANK_BASE+0x494)
+#define RB_CLK_DIV_ARM (MARIA_REGBANK_BASE+0x498)
+#define RB_CLK_DIV_STAT_ARM (MARIA_REGBANK_BASE+0x49C)
+#define CLK_DIV_ARM_2 (0x0)
+#define CLK_DIV_ARM_4 (0x1)
+#define CLK_DIV_SYS_4 (0x0)
+#define RB_CLK_CMD_SRAM (MARIA_REGBANK_BASE+0x4A0)
+#define RB_CLK_STAT_SRAM (MARIA_REGBANK_BASE+0x4A4)
+#define RB_CLK_DIV_SRAM (MARIA_REGBANK_BASE+0x4A8)
+#define RB_CLK_DIV_STAT_SRAM (MARIA_REGBANK_BASE+0x4AC)
+#define CLK_DIV_SRAM_8 (0x0)
+#define CLK_DIV_SRAM_12 (0x1)
+#define CLK_DIV_SRAM_16 (0x2)
+#define RB_CLK_CMD_MPG_EXT (MARIA_REGBANK_BASE+0x4B0)
+#define RB_CLK_STAT_MPG_EXT (MARIA_REGBANK_BASE+0x4B4)
+#define RB_CLK_CMD_MPG_INT (MARIA_REGBANK_BASE+0x4C0)
+#define RB_CLK_STAT_MPG_INT (MARIA_REGBANK_BASE+0x4C4)
+#define RB_CLK_DIV_MPG_INT (MARIA_REGBANK_BASE+0x4C8)
+#define RB_CLK_DIV_STAT_MPG_INT (MARIA_REGBANK_BASE+0x4CC)
+#define RB_CLK_SEL_MPG (MARIA_REGBANK_BASE+0x4D0)
+#define RB_CLK_SEL_STAT_MPG (MARIA_REGBANK_BASE+0x4D4)
+#define CLK_SEL_MPG_INT (0x0)
+#define CLK_SEL_MPG_EXT (0x1)
+#define RB_CLK_CMD_SPI (MARIA_REGBANK_BASE+0x4E0)
+#define RB_CLK_STAT_SPI (MARIA_REGBANK_BASE+0x4E4)
+#define RB_CLK_CMD_I2S (MARIA_REGBANK_BASE+0x4F0)
+#define RB_CLK_STAT_I2S (MARIA_REGBANK_BASE+0x4F4)
+#define RB_CLK_DIV_I2S (MARIA_REGBANK_BASE+0x4F8)
+#define RB_CLK_DIV_STAT_I2S (MARIA_REGBANK_BASE+0x4FC)
+#define RB_CLK_CMD_PCM (MARIA_REGBANK_BASE+0x500)
+#define RB_CLK_STAT_PCM (MARIA_REGBANK_BASE+0x504)
+#define RB_CLK_DIV_PCM (MARIA_REGBANK_BASE+0x508)
+#define RB_CLK_DIV_STAT_PCM (MARIA_REGBANK_BASE+0x50C)
+#define RB_CLK_DIV_T1 (MARIA_REGBANK_BASE+0x518)
+#define RB_CLK_DIV_STAT_T1 (MARIA_REGBANK_BASE+0x51C)
+#define RB_CLK_DIV_T2 (MARIA_REGBANK_BASE+0x528)
+#define RB_CLK_DIV_STAT_T2 (MARIA_REGBANK_BASE+0x52C)
+#define RB_PPLL_FBDIV (MARIA_REGBANK_BASE+0x530)
+#define RB_PPLL_PREDIV (MARIA_REGBANK_BASE+0x534)
+#define RB_PPLL_LBWS (MARIA_REGBANK_BASE+0x538)
+#define RB_PPLL_PD (MARIA_REGBANK_BASE+0x53C)
+#define RB_PPLL_BYPASS (MARIA_REGBANK_BASE+0x540)
+#define RB_PPLL_BYPASS_STAT (MARIA_REGBANK_BASE+0x544)
+#define RB_PPLL_DEBUG (MARIA_REGBANK_BASE+0x548)
+#define RB_DPLL_FBDIV (MARIA_REGBANK_BASE+0x550)
+#define RB_DPLL_PREDIV (MARIA_REGBANK_BASE+0x554)
+#define RB_DPLL_LBWS (MARIA_REGBANK_BASE+0x558)
+#define RB_DPLL_PD (MARIA_REGBANK_BASE+0x55C)
+#define RB_DPLL_BYPASS (MARIA_REGBANK_BASE+0x560)
+#define RB_DPLL_BYPASS_STAT (MARIA_REGBANK_BASE+0x564)
+#define RB_DPLL_DEBUG (MARIA_REGBANK_BASE+0x568)
+#define RB_SPLL_FBDIV (MARIA_REGBANK_BASE+0x570)
+#define RB_SPLL_PREDIV (MARIA_REGBANK_BASE+0x574)
+#define RB_SPLL_LBWS (MARIA_REGBANK_BASE+0x578)
+#define RB_SPLL_PD (MARIA_REGBANK_BASE+0x57C)
+#define RB_SPLL_BYPASS (MARIA_REGBANK_BASE+0x580)
+#define RB_SPLL_BYPASS_STAT (MARIA_REGBANK_BASE+0x584)
+#define RB_SPLL_FCW (MARIA_REGBANK_BASE+0x588)
+#define RB_SPLL_FMW (MARIA_REGBANK_BASE+0x58C)
+#define RB_SPLL_MDW (MARIA_REGBANK_BASE+0x590)
+#define RB_SPLL_EN (MARIA_REGBANK_BASE+0x594)
+#define RB_SPLL_DEBUG (MARIA_REGBANK_BASE+0x598)
+#define RB_SPLL_SSCGNRST (MARIA_REGBANK_BASE+0x59C)
+#define RB_CLK_CMD_SDR (MARIA_REGBANK_BASE+0x5A0)
+#define RB_CLK_STAT_SDR (MARIA_REGBANK_BASE+0x5A4)
+#define RB_CLK_CMD_OUT25 (MARIA_REGBANK_BASE+0x5B0)
+#define RB_CLK_STAT_OUT25 (MARIA_REGBANK_BASE+0x5B4)
+#define RB_PWM_ENABLE (MARIA_REGBANK_BASE+0x600)
+#define RB_PWM_PERIOD_0 (MARIA_REGBANK_BASE+0x604)
+#define RB_PWM_PERIOD_1 (MARIA_REGBANK_BASE+0x608)
+#define RB_PWM_PERIOD_2 (MARIA_REGBANK_BASE+0x60C)
+#define RB_PWM_PERIOD_3 (MARIA_REGBANK_BASE+0x610)
+#define RB_PWM_PULSE_0 (MARIA_REGBANK_BASE+0x614)
+#define RB_PWM_PULSE_1 (MARIA_REGBANK_BASE+0x618)
+#define RB_PWM_PULSE_2 (MARIA_REGBANK_BASE+0x61C)
+#define RB_PWM_PULSE_3 (MARIA_REGBANK_BASE+0x620)
+#define RB_ETH_CONFIG (MARIA_REGBANK_BASE+0x630)
+#define RB_RST_GSRC (MARIA_REGBANK_BASE+0x700)
+#define RST_GSRC_POWER (0x1)
+#define RST_GSRC_EXT (0x2)
+#define RST_GSRC_WDOG (0x4)
+#define RST_GSRC_SOFT (0x8)
+#define RB_RST_GLOBAL (MARIA_REGBANK_BASE+0x704)
+#define RST_GLOBAL (0x1)
+#define RB_RST_GROUP (MARIA_REGBANK_BASE+0x708)
+#define RST_SYS (0x1)
+#define RST_INTF (0x2)
+#define RST_DSP (0x4)
+#define RST_LEONSS (0x8)
+#define RB_RST_MODULE (MARIA_REGBANK_BASE+0x70C)
+#define RST_ARM (0x1)
+#define RST_GPDMA (0x2)
+#define RST_ARM_APB (0x4)
+#define RST_SPI (0x8)
+#define RST_PCM (0x10)
+#define RST_SRAM (0x20)
+#define RST_I2S (0x40)
+#define RST_MBOX (0x80)
+#define RST_ETH (0x100)
+#define RST_MPG (0x200)
+#define RST_DMAB (0x400)
+#define RST_LCPU (0x800)
+#define RST_EXT (0x1000)
+#define RB_RST_GMASK (MARIA_REGBANK_BASE+0x710)
+#define RB_FCM3_UART_SELECT (MARIA_REGBANK_BASE+0x800)
+#define RB_FCM3_AD_SPIEN (MARIA_REGBANK_BASE+0x804)
+
+#endif /* __ASM_ARCH_PKG_MARIA_REGBANK_H */