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authorAleksandar Cecaric2013-08-20 17:02:23 +0200
committerAleksandar Cecaric2013-08-23 16:30:35 +0200
commit42271a171cff3741cc7789755617e186fadb9816 (patch)
treed3132f9c70a26681124f5a73e0509c37176de1e2 /cleopatre
parentce16d2f171d870434a3c3b0fb23b3ac30deee963 (diff)
{cleo/uboot/cpu/spc300,common}: take rmii clock from the phy, refs #4157
Diffstat (limited to 'cleopatre')
-rw-r--r--cleopatre/u-boot-1.1.6/cpu/spc300/mseeth.S30
1 files changed, 30 insertions, 0 deletions
diff --git a/cleopatre/u-boot-1.1.6/cpu/spc300/mseeth.S b/cleopatre/u-boot-1.1.6/cpu/spc300/mseeth.S
index ba282a959c..9aa081ff51 100644
--- a/cleopatre/u-boot-1.1.6/cpu/spc300/mseeth.S
+++ b/cleopatre/u-boot-1.1.6/cpu/spc300/mseeth.S
@@ -181,6 +181,12 @@ ethernet_config:
setreg RB_CLK_DIV_ETH1_TX_PLL_OFFSET, CLK_ETH_DIV_TX_PLL_10, r0, r2
setreg RB_CLK_DIV_ETH1_RX_PLL_OFFSET, CLK_ETH_DIV_RX_PLL_10, r0, r2
+ /* Check clock source. */
+ ldr r3, =IOMUX_BASE
+ ldr r2, [r3, #IOMUX_GLOBAL_ETH_OFFSET]
+ eors r2, #IOMUX_RMII_PHY_CLOCK_ENABLE
+ beq 1f
+
/* Enable TX clock */
setreg RB_CLK_SEL_ETH1_TX_OFFSET, CLK_SEL_ETH_TX_RX_PLL_CLK, r0, r2
checkreg RB_CLK_SEL_STAT_ETH1_TX_OFFSET, CLK_SEL_ETH_TX_RX_PLL_CLK, r0, r2
@@ -203,6 +209,30 @@ ethernet_config:
checkreg RB_CLK_STAT_ETH1_RMII_OFFSET, CLK_ETH_RMII_PLL_IS_ON, r0, r2
endconfig r1, r2
+1:
+ /* Use RMII clock from PHY. */
+ /* Enable TX clock */
+ setreg RB_CLK_SEL_ETH1_TX_OFFSET, CLK_SEL_ETH_TX_RX_RMII_CLK, r0, r2
+ checkreg RB_CLK_SEL_STAT_ETH1_TX_OFFSET, CLK_SEL_ETH_TX_RX_RMII_CLK, r0, r2
+
+ setreg RB_CLK_CMD_ETH1_TX_OFFSET, CLK_CMD_RMII_ON, r0, r2
+ checkreg RB_CLK_STAT_ETH1_TX_OFFSET, CLK_ETH_TX_RX_RMII_IS_ON, r0, r2
+
+ /* Enable RX clock */
+ setreg RB_CLK_SEL_ETH1_RX_OFFSET, CLK_SEL_ETH_TX_RX_RMII_CLK, r0, r2
+ checkreg RB_CLK_SEL_STAT_ETH1_RX_OFFSET, CLK_SEL_ETH_TX_RX_RMII_CLK, r0, r2
+
+ setreg RB_CLK_CMD_ETH1_RX_OFFSET, CLK_CMD_RMII_ON, r0, r2
+ checkreg RB_CLK_STAT_ETH1_RX_OFFSET, CLK_ETH_TX_RX_RMII_IS_ON, r0, r2
+
+ /* Enable RMII clock */
+ setreg RB_CLK_SEL_ETH1_RMII_OFFSET, CLK_SEL_ETH_RMII_RMII_CLK, r0, r2
+ checkreg RB_CLK_SEL_STAT_ETH1_RMII_OFFSET, CLK_SEL_ETH_RMII_RMII_CLK, r0, r2
+
+ setreg RB_CLK_CMD_ETH1_RMII_OFFSET, CLK_CMD_RMII_PLL_ON, r0, r2
+ checkreg RB_CLK_STAT_ETH1_RMII_OFFSET, CLK_ETH_RMII_PLL_IS_ON, r0, r2
+
+ endconfig r1, r2
.Lgmii:
/*