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authorNicolas Schodet2012-04-05 08:56:41 +0200
committerNicolas Schodet2012-04-10 16:19:12 +0200
commit5d8995787a4d419663b003958a3e02c1874c74d3 (patch)
tree0625204f5ca6510160298eb16479c07609c86c83 /cleopatre/u-boot-1.1.6
parent544ffebf5850f4b5b74b1b5dd4c7cb08e1647669 (diff)
cleopatre/u-boot: raise SPI speed to 18.375 MHz, closes #3067
Speed computed for the maximum master clock, better setup will be done with mse500 commits.
Diffstat (limited to 'cleopatre/u-boot-1.1.6')
-rw-r--r--cleopatre/u-boot-1.1.6/board/sdk300/flash.c2
-rw-r--r--cleopatre/u-boot-1.1.6/cpu/spc300/start.S2
2 files changed, 2 insertions, 2 deletions
diff --git a/cleopatre/u-boot-1.1.6/board/sdk300/flash.c b/cleopatre/u-boot-1.1.6/board/sdk300/flash.c
index 1358ec29b4..78563dc7c6 100644
--- a/cleopatre/u-boot-1.1.6/board/sdk300/flash.c
+++ b/cleopatre/u-boot-1.1.6/board/sdk300/flash.c
@@ -238,7 +238,7 @@ void init_spi_controller(void)
SPI_CTL_MASTER_SLAVE_REG = 0x01; /* Master */
SPI_CTL_CONTROL_CONFIG_REG = 0x00; /* 3 wires Master */
- SPI_CTL_FREQ_REG = 0x04; /* 18.75 Mhz (MARIA_MASTER_CLOCK/8) */
+ SPI_CTL_FREQ_REG = 0x03; /* 18.375 Mhz (MARIA_MASTER_CLOCK/8 @147MHz) */
SPI_CTL_CS_LATENCY = 0x04; /* 4 cycles clock AHB */
SPI_CTL_CONF_TX = 0x00010008; /* send one byte (i.e. one word of length of 8 bits) */
SPI_CTL_CONF_RX = 0x00010008; /* receive one byte */
diff --git a/cleopatre/u-boot-1.1.6/cpu/spc300/start.S b/cleopatre/u-boot-1.1.6/cpu/spc300/start.S
index 47242c47cc..f4c75003a8 100644
--- a/cleopatre/u-boot-1.1.6/cpu/spc300/start.S
+++ b/cleopatre/u-boot-1.1.6/cpu/spc300/start.S
@@ -342,7 +342,7 @@ cpu_init_crit:
* Speed up SPI and ARM
*/
ldr r0, =SPI_FREQ
- ldr r1, =0x00000005 /* divide CLK_AHB (after PLL) by 12 (<20MHz)*/
+ ldr r1, =0x00000003 /* divide CLK_AHB (after PLL) by 8 (<20MHz @147MHz)*/
str r1, [r0]
ldr r0, =REGBANK_BASE