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authorsave2009-08-26 08:31:20 +0000
committersave2009-08-26 08:31:20 +0000
commit272490c88233979bd259d7a11a5de462d3cf9bd3 (patch)
treec785f29805080c11d4b5620522ae86c2acf77b46 /cleopatre/u-boot-1.1.6/cpu/spc300
parent06401fd9387d165675d359c59d03094f016df692 (diff)
[CLEO][NVRAM]Added a gpio_allow_dir field under NVRAM
git-svn-id: svn+ssh://pessac/svn/cesar/trunk@5297 017c9cb6-072f-447c-8318-d5b54f68fe89
Diffstat (limited to 'cleopatre/u-boot-1.1.6/cpu/spc300')
-rw-r--r--cleopatre/u-boot-1.1.6/cpu/spc300/nvram.S1
-rw-r--r--cleopatre/u-boot-1.1.6/cpu/spc300/start.S10
2 files changed, 6 insertions, 5 deletions
diff --git a/cleopatre/u-boot-1.1.6/cpu/spc300/nvram.S b/cleopatre/u-boot-1.1.6/cpu/spc300/nvram.S
index 1a2c0254e0..ff6bfc56db 100644
--- a/cleopatre/u-boot-1.1.6/cpu/spc300/nvram.S
+++ b/cleopatre/u-boot-1.1.6/cpu/spc300/nvram.S
@@ -106,6 +106,7 @@ nvram_dft:
.word 0x0000020c /* pkg_cfg */
.word 0x00000000 /* gpio_0_7_cfg */
.word 0x00000000 /* gpio_8_15_cfg */
+ .word 0xffffffff /* gpio_allow_dir*/
.word 0x001c3168 /* sdram_config */
.word 0x022a569a /* sdram_timing0 */
.word 0x00070008 /* sdram_timing1 */
diff --git a/cleopatre/u-boot-1.1.6/cpu/spc300/start.S b/cleopatre/u-boot-1.1.6/cpu/spc300/start.S
index 95e1b9b2b6..12d8c274b3 100644
--- a/cleopatre/u-boot-1.1.6/cpu/spc300/start.S
+++ b/cleopatre/u-boot-1.1.6/cpu/spc300/start.S
@@ -349,25 +349,25 @@ poll_RB_CLK_DIV_STAT_ARM:
/* set up return latency, needed for system clock */
ldr r0, =REGBANK_BASE
mov r1, #1
- str r1, [r10, #RB_SDRAM_RETURN_LAT]
+ str r1, [r0, #RB_SDRAM_RETURN_LAT]
/* do sdram init */
ldr r1, =SDRAM_CTRL_BASE
/* SCONR */
- ldr r2, [r10, #20] /* load SCONR content from NVRAM */
+ ldr r2, [r10, #24] /* load SCONR content from NVRAM */
str r2, [r1, #SCONR] /* store configuration to config reg */
/* STMG0R */
- ldr r2, [r10, #24] /* load STMG0R content from NVRAM */
+ ldr r2, [r10, #28] /* load STMG0R content from NVRAM */
str r2, [r1, #STMG0R] /* store configuration to config reg */
/* STMG1R */
- ldr r2, [r10, #28] /* load STMG1R content from NVRAM */
+ ldr r2, [r10, #32] /* load STMG1R content from NVRAM */
str r2, [r1, #STMG1R] /* store configuration to config reg */
/* SREFR */
- ldr r2, [r10, #32] /* load SREFR content from NVRAM */
+ ldr r2, [r10, #36] /* load SREFR content from NVRAM */
str r2, [r1, #SREFR] /* store configuration to config reg */
/* Find Freq parameters from NVRAM (struct address is in r10) */