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authorCyril Jourdan2012-08-23 16:31:44 +0200
committerCyril Jourdan2012-09-20 11:23:18 +0200
commit14d2863e4c73dc8406d34758ca0081143453dc1b (patch)
treeff406afe6d584787b0c2dc3753e9d05f90d59386 /cleopatre/u-boot-1.1.6/cpu/spc300/masterclk.c
parentdd0ea876f3c0341d16cf3a383830542eebec01cf (diff)
cleo/uboot/cpu/spc300: make get_master_clock common, refs #2961
Diffstat (limited to 'cleopatre/u-boot-1.1.6/cpu/spc300/masterclk.c')
-rw-r--r--cleopatre/u-boot-1.1.6/cpu/spc300/masterclk.c79
1 files changed, 79 insertions, 0 deletions
diff --git a/cleopatre/u-boot-1.1.6/cpu/spc300/masterclk.c b/cleopatre/u-boot-1.1.6/cpu/spc300/masterclk.c
new file mode 100644
index 0000000000..1e843acc7e
--- /dev/null
+++ b/cleopatre/u-boot-1.1.6/cpu/spc300/masterclk.c
@@ -0,0 +1,79 @@
+/*
+ * cpu/spc300/masterclk.c
+ *
+ * Copyright (C) 2012 SPiDCOM Technologies
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <config.h>
+#include <asm/arch/nvram.h>
+
+/**
+ * Get master clock from NVRAM
+ *
+ * \return master clock value in Hz.
+ */
+ulong get_master_clock(void)
+{
+ ulong masterclk;
+
+#ifdef CONFIG_CHIP_FEATURE_FIXED_MASTER_CLOCK
+
+ masterclk = CONFIG_CHIP_MAX_MASTER_CLOCK;
+
+#else
+
+ DECLARE_GLOBAL_DATA_PTR;
+ bd_t *bd = gd->bd;
+ spidcom_nvram_t *nvram = (spidcom_nvram_t*)bd->bi_nvram_addr;
+
+#ifdef CONFIG_CHIP_MSE500
+ switch(NVRAM_BFEXT(MSE500_MODE, nvram->pkg_cfg))
+ {
+ case NVRAM_MSE500_MODE_200:
+ masterclk = 96000000;
+ break;
+ case NVRAM_MSE500_MODE_300:
+ case NVRAM_MSE500_MODE_500:
+ default:
+ masterclk = 246000000;
+ break;
+ }
+#else
+ switch(NVRAM_BFEXT(FREQ, nvram->pkg_cfg))
+ {
+ case NVRAM_FREQ_100:
+ masterclk = 100000000;
+ break;
+ case NVRAM_FREQ_125:
+ masterclk = 125000000;
+ break;
+ case NVRAM_FREQ_133:
+ masterclk = 133000000;
+ break;
+ case NVRAM_FREQ_150:
+ default:
+ masterclk = 147000000;
+ break;
+ }
+#endif /* CONFIG_CHIP_MSE500 */
+
+#endif /* CONFIG_CHIP_FEATURE_FIXED_MASTER_CLOCK */
+
+ return masterclk;
+}