summaryrefslogtreecommitdiff
path: root/cleopatre/u-boot-1.1.6/common
diff options
context:
space:
mode:
authorCyril Jourdan2013-01-29 10:51:11 +0100
committerCyril Jourdan2013-02-05 15:57:25 +0100
commitcfeadd2d973639a0e467c9d27bbd797231e2eafa (patch)
treeffc785fb08f6d25c5078742409647c34ad9aac08 /cleopatre/u-boot-1.1.6/common
parent0fbc678ae8cc3ba03b7ba2db9a8d51e58a5d8713 (diff)
cleo/uboot/cmd_spidboot: set DSP PLL just before boot, refs #3694
Diffstat (limited to 'cleopatre/u-boot-1.1.6/common')
-rw-r--r--cleopatre/u-boot-1.1.6/common/cmd_spidboot.c76
1 files changed, 75 insertions, 1 deletions
diff --git a/cleopatre/u-boot-1.1.6/common/cmd_spidboot.c b/cleopatre/u-boot-1.1.6/common/cmd_spidboot.c
index 1825cf4dba..55ca070aa3 100644
--- a/cleopatre/u-boot-1.1.6/common/cmd_spidboot.c
+++ b/cleopatre/u-boot-1.1.6/common/cmd_spidboot.c
@@ -35,6 +35,7 @@
#include <asm/arch/ips/uart.h>
#if defined (CONFIG_CHIP_MSE500)
#include <asm/arch/ips/hardware/msepll.h>
+#include <asm/arch/ips/hardware/mseafe.h>
#include <asm/arch/ips/hardware/pkg_maria2_regbank.h>
#endif /* CONFIG_CHIP_MSE500 */
@@ -272,6 +273,78 @@ static void setup_system_pll (uint32_t speed, uint32_t type)
setup_uart (speed);
}
+
+/*
+ * This function sets the DSP PLL speed. Value is determined depending on
+ * the image type and the mode in NVRAM.
+ */
+static void setup_dsp_pll (uint32_t type)
+{
+ spidcom_nvram_t *nvram = (spidcom_nvram_t *)(gd->bd->bi_nvram_addr);
+ int adc_div, dsp_div, dac_div, loop_div, icp;
+
+ if (type == SPIDCOM_IMG_DESC_IMAGE_TYPE_200)
+ {
+ /* Config for an output clock at 256 MHz.
+ * DSP clock is 128 MHz due to a divisor after the PLL output. */
+ adc_div = MSEAFE_DPLL_CTRL_ADC_DIV_6;
+ dsp_div = MSEAFE_DPLL_CONF_DSP_DIV_3;
+ dac_div = MSEAFE_DPLL_CONF_DAC_DIV_3;
+ loop_div = 32;
+ icp = 3;
+ }
+ else
+ {
+ /* Config for an output clock at 300 MHz.
+ * DSP clock is 150 MHz due to a divisor after the PLL output in
+ * 300 mode. In 500 mode, divisor is bypassed to get a DSP clock at
+ * 300 MHz. */
+ adc_div = MSEAFE_DPLL_CTRL_ADC_DIV_4;
+ dsp_div = MSEAFE_DPLL_CONF_DSP_DIV_2;
+ dac_div = MSEAFE_DPLL_CONF_DAC_DIV_2;
+ loop_div = 25;
+ icp = 2;
+
+ if (NVRAM_BFEXT (MSE500_MODE, nvram->pkg_cfg) == NVRAM_MSE500_MODE_500)
+ *((volatile uint32_t *)(MARIA_REGBANK_BASE + RB_CLK_DIV_DSP_OFFSET)) = CLK_DIV_DSP_1;
+ }
+
+ *((volatile uint32_t *)RB_DPLL_BYPASS) = PLL_CMD_BYPASS;
+ while (*((volatile uint32_t *)RB_DPLL_BYPASS_STAT) != PLL_IS_BYPASS)
+ ;
+
+ *((volatile uint32_t *)(MSEAFE_BASE + MSEAFE_DPLL_CONF_OFFSET)) |= MSEAFE_BIT (DPLL_CONF_PD);
+ *((volatile uint32_t *)(MSEAFE_BASE + MSEAFE_DPLL_CTRL_OFFSET)) |= MSEAFE_BIT (DPLL_CTRL_PD_CLK);
+ *((volatile uint32_t *)(MSEAFE_BASE + MSEAFE_DPLL_CTRL_OFFSET)) |= MSEAFE_BIT (DPLL_CTRL_PD_DAC_CLK_OUT);
+ *((volatile uint32_t *)(MSEAFE_BASE + MSEAFE_DPLL_CTRL_OFFSET)) |= MSEAFE_BIT (DPLL_CTRL_PD_DAC_CLK);
+ *((volatile uint32_t *)(MSEAFE_BASE + MSEAFE_DPLL_CTRL_OFFSET)) |= MSEAFE_BIT (DPLL_CTRL_PD_ADC_CLK);
+
+ *((volatile uint32_t *)(MSEAFE_BASE + MSEAFE_DPLL_CTRL_OFFSET)) =
+ MSEAFE_BFINS (DPLL_CTRL_REF_DIV, MSEAFE_DPLL_CTRL_REF_DIV_2, *((volatile uint32_t *)(MSEAFE_BASE + MSEAFE_DPLL_CTRL_OFFSET)));
+ *((volatile uint32_t *)(MSEAFE_BASE + MSEAFE_DPLL_CTRL_OFFSET)) =
+ MSEAFE_BFINS (DPLL_CTRL_ADC_DIV, adc_div, *((volatile uint32_t *)(MSEAFE_BASE + MSEAFE_DPLL_CTRL_OFFSET)));
+ *((volatile uint32_t *)(MSEAFE_BASE + MSEAFE_DPLL_LOOP_DIV_OFFSET)) =
+ MSEAFE_BFINS (DPLL_LOOP_DIV_FIRST, MSEAFE_DPLL_LOOP_DIV_FIRST_2, *((volatile uint32_t *)(MSEAFE_BASE + MSEAFE_DPLL_LOOP_DIV_OFFSET)));
+ *((volatile uint32_t *)(MSEAFE_BASE + MSEAFE_DPLL_LOOP_DIV_OFFSET)) =
+ MSEAFE_BFINS (DPLL_LOOP_DIV_SECOND, loop_div, *((volatile uint32_t *)(MSEAFE_BASE + MSEAFE_DPLL_LOOP_DIV_OFFSET)));
+ *((volatile uint32_t *)(MSEAFE_BASE + MSEAFE_DPLL_CONF_OFFSET)) =
+ MSEAFE_BFINS (DPLL_CONF_DSP_DIV, dsp_div, *((volatile uint32_t *)(MSEAFE_BASE + MSEAFE_DPLL_CONF_OFFSET)));
+ *((volatile uint32_t *)(MSEAFE_BASE + MSEAFE_DPLL_CONF_OFFSET)) =
+ MSEAFE_BFINS (DPLL_CONF_DAC_DIV, dac_div, *((volatile uint32_t *)(MSEAFE_BASE + MSEAFE_DPLL_CONF_OFFSET)));
+ *((volatile uint32_t *)(MSEAFE_BASE + MSEAFE_DPLL_CONF_OFFSET)) =
+ MSEAFE_BFINS (DPLL_CONF_ICP, icp, *((volatile uint32_t *)(MSEAFE_BASE + MSEAFE_DPLL_CONF_OFFSET)));
+
+ *((volatile uint32_t *)(MSEAFE_BASE + MSEAFE_DPLL_CTRL_OFFSET)) &= ~MSEAFE_BIT (DPLL_CTRL_PD_ADC_CLK);
+ *((volatile uint32_t *)(MSEAFE_BASE + MSEAFE_DPLL_CTRL_OFFSET)) &= ~MSEAFE_BIT (DPLL_CTRL_PD_DAC_CLK);
+ *((volatile uint32_t *)(MSEAFE_BASE + MSEAFE_DPLL_CTRL_OFFSET)) &= ~MSEAFE_BIT (DPLL_CTRL_PD_DAC_CLK_OUT);
+ *((volatile uint32_t *)(MSEAFE_BASE + MSEAFE_DPLL_CTRL_OFFSET)) &= ~MSEAFE_BIT (DPLL_CTRL_PD_CLK);
+ *((volatile uint32_t *)(MSEAFE_BASE + MSEAFE_DPLL_CONF_OFFSET)) &= ~MSEAFE_BIT (DPLL_CONF_PD);
+
+ *((volatile uint32_t *)RB_DPLL_BYPASS) = PLL_CMD_PLL;
+ while (*((volatile uint32_t *)RB_DPLL_BYPASS_STAT) != PLL_IS_PLL)
+ ;
+}
+
#endif /* CONFIG_CHIP_MSE500 */
/* --- SPiDBOOT --- */
@@ -788,8 +861,9 @@ int do_spidboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
#endif
#if defined (CONFIG_CHIP_MSE500)
- /* Before booting Linux, we need to set the System PLL. */
+ /* Before booting Linux, we need to set System and DSP PLL. */
setup_system_pll (hdr->header->sysclk_speed, hdr->header->image_type);
+ setup_dsp_pll (hdr->header->image_type);
#endif
/* disable D/I caches and flush them */