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authorOlivier Dufour2012-11-14 17:34:53 +0100
committerOlivier Dufour2012-12-21 15:15:43 +0100
commit2a7776d506ef183e19962857eb0b5d6ff642a8df (patch)
tree9f5a0986a6d1d524d37c88a597fdfd4bc8713b78 /cleopatre/linux-2.6.25.10-spc300/arch
parentd8bef8edd5f921e857ddf4e877058e0ab565b3e5 (diff)
cleo/linux/arch/arm/spc300: put SDRAM in self-refresh mode, refs #2633
Diffstat (limited to 'cleopatre/linux-2.6.25.10-spc300/arch')
-rw-r--r--cleopatre/linux-2.6.25.10-spc300/arch/arm/mach-spc300/spc300.c1
-rw-r--r--cleopatre/linux-2.6.25.10-spc300/arch/arm/mach-spc300/sram.S102
2 files changed, 100 insertions, 3 deletions
diff --git a/cleopatre/linux-2.6.25.10-spc300/arch/arm/mach-spc300/spc300.c b/cleopatre/linux-2.6.25.10-spc300/arch/arm/mach-spc300/spc300.c
index 8d6b61adbd..cbe9982c0f 100644
--- a/cleopatre/linux-2.6.25.10-spc300/arch/arm/mach-spc300/spc300.c
+++ b/cleopatre/linux-2.6.25.10-spc300/arch/arm/mach-spc300/spc300.c
@@ -86,6 +86,7 @@ static struct map_desc spc300_io_desc[] __initdata = {
{ IO_ADDRESS(MARIA_REGBANK_BASE) , __phys_to_pfn(MARIA_REGBANK_BASE) , SZ_4K , MT_DEVICE },
#ifdef CONFIG_CHIP_FEATURE_MIU_CTRL
{ IO_ADDRESS(AHB2MIU_BASE) , __phys_to_pfn(AHB2MIU_BASE) , SZ_1K , MT_DEVICE },
+ { IO_ADDRESS(MIU_BASE) , __phys_to_pfn(MIU_BASE) , SZ_8K , MT_DEVICE },
#endif
{ IO_ADDRESS(ARM_GPIO_BASE) , __phys_to_pfn(ARM_GPIO_BASE) , SZ_1K , MT_DEVICE },
{ IO_ADDRESS(ARM_WDT_BASE) , __phys_to_pfn(ARM_WDT_BASE) , SZ_1K , MT_DEVICE },
diff --git a/cleopatre/linux-2.6.25.10-spc300/arch/arm/mach-spc300/sram.S b/cleopatre/linux-2.6.25.10-spc300/arch/arm/mach-spc300/sram.S
index 75ad3e8923..e4e76644fe 100644
--- a/cleopatre/linux-2.6.25.10-spc300/arch/arm/mach-spc300/sram.S
+++ b/cleopatre/linux-2.6.25.10-spc300/arch/arm/mach-spc300/sram.S
@@ -30,8 +30,9 @@
.globl pm_process
.type pm_process, %function
-/* Counter to repeat group of NB_INSTR instructions to reach 600uS time. */
-/* (((time_to_wait * Xclk) / 1000000) / cpu_cycles_nb) */
+/* Counter to repeat group of NB_INSTR instructions to reach a defined amount
+ * of time : (((time_to_wait * current clock) / 1000000) / cpu_cycles_nb) */
+#define MIU_WAIT_TIME 99 /* (((1 * 492000000) / 1000000) / 5) */
#define PLL_WAIT_TIME 2880 /* (((600 * 24000000) / 1000000) / 5) */
/* This macro is used to clear bits in an IP register. */
@@ -62,7 +63,70 @@
pm_process:
/* Save registers that we will use. */
push {r1, r2}
-
+
+ /* Flush TLB. */
+ mov r0, #0
+ mcr p15, 0, r0, c8, c7, 0
+
+ /* Dummy reads to fill TLB with the pages we will use after SDRAM
+ * deactivation. This is needed to ensure that there will not be any
+ * access to SDRAM once it is in self-refresh mode. */
+ ldr r0, =IO_ADDRESS(MIU_BASE)
+ ldr r1, [r0]
+ ldr r0, =IO_ADDRESS(MARIA_REGBANK_BASE)
+ ldr r1, [r0]
+ ldr r0, =IO_ADDRESS(EXT_REG_BANK_BASE) + MSEPLL_SPLL_OFFSET
+ ldr r1, [r0]
+ ldr r0, =IO_ADDRESS(EXT_REG_BANK_BASE) + MSEPLL_PPLL_OFFSET
+ ldr r1, [r0]
+ ldr r0, =IO_ADDRESS(EXT_REG_BANK_BASE) + MSEAFE_OFFSET
+ ldr r1, [r0]
+ ldr r0, =IO_ADDRESS(ARM_WDT_BASE)
+ ldr r1, [r0]
+ ldr r0, =IO_ADDRESS(ARM_ICTL_BASE)
+ ldr r1, [r0]
+
+ /* Put MIU into self-refresh mode. */
+ ldr r0, =IO_ADDRESS(MIU_BASE)
+ mov r1, #0x0
+ str r1, [r0, #0x1d0]
+ ldr r1, =0xfffe
+ str r1, [r0, #0x8c]
+ ldr r1, =0xffff
+ str r1, [r0, #0xcc]
+ str r1, [r0, #0x10c]
+ str r1, [r0, #0x14c]
+ ldr r2, =MIU_WAIT_TIME
+1:
+ sub r2, r2, #1
+ cmp r2, #0
+ bne 1b
+ ldr r1, =0x400
+ str r1, [r0, #0x30]
+ ldr r1, =0x2f
+ str r1, [r0, #0x0]
+ ldr r1, =0x1420
+ str r1, [r0, #0xc]
+ ldr r1, =0x52e
+ str r1, [r0, #0x0]
+ ldr r1, =0x2e
+ str r1, [r0, #0x0]
+ ldr r1, =0x32e
+ str r1, [r0, #0x0]
+ ldr r1, =0x2e
+ str r1, [r0, #0x0]
+ ldr r2, =MIU_WAIT_TIME
+1:
+ sub r2, r2, #1
+ cmp r2, #0
+ bne 1b
+ ldr r1, =0xffff
+ str r1, [r0, #0x8c]
+ ldr r1, =0x202e
+ str r1, [r0, #0x0]
+ ldr r1, =0xe2a2
+ str r1, [r0, #0x4]
+
/*
* Bypass PLLs. We keep Peripheral PLL alive for ETH PHY and GMAC.
*/
@@ -161,6 +225,38 @@ pm_process:
str r1, [r0, #RB_DPLL_BYPASS_OFFSET]
waitstatus r0, RB_DPLL_BYPASS_STAT_OFFSET, PLL_IS_PLL, r2
+ /* Put MIU back into auto-refresh mode. */
+ ldr r0, =IO_ADDRESS(MIU_BASE)
+ ldr r1, =0x2a2
+ str r1, [r0, #0x4]
+ ldr r1, =0x2e
+ str r1, [r0, #0x0]
+ ldr r1, =0xfffe
+ str r1, [r0, #0x8c]
+ ldr r2, =MIU_WAIT_TIME
+1:
+ sub r2, r2, #1
+ cmp r2, #0
+ bne 1b
+ ldr r1, =0x32e
+ str r1, [r0, #0x0]
+ ldr r1, =0x2e
+ str r1, [r0, #0x0]
+ ldr r1, =0xe
+ str r1, [r0, #0x0]
+ ldr r2, =MIU_WAIT_TIME
+1:
+ sub r2, r2, #1
+ cmp r2, #0
+ bne 1b
+ ldr r1, =0x420
+ str r1, [r0, #0xc]
+ ldr r1, =0x0
+ str r1, [r0, #0x8c]
+ str r1, [r0, #0xcc]
+ str r1, [r0, #0x10c]
+ str r1, [r0, #0x14c]
+
/* Restore registers. */
pop {r1, r2}