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authorCyril Jourdan2012-08-21 10:40:44 +0200
committerCyril Jourdan2012-09-20 11:21:14 +0200
commit0ecb4b0db0d079c74839162dad4cedd7c9ffc85d (patch)
treed21bf062730d65b57d60c3ec9a95539942b52707 /cleopatre/devkit/tests/libspid/utests/src/system_utests.c
parentfb82d1282951af2696829d013c6ec9131069866a (diff)
common/inc/asm/arch: pack IOMUX & GPIO config in same NVRAM fields, refs #2961
Diffstat (limited to 'cleopatre/devkit/tests/libspid/utests/src/system_utests.c')
-rw-r--r--cleopatre/devkit/tests/libspid/utests/src/system_utests.c18
1 files changed, 9 insertions, 9 deletions
diff --git a/cleopatre/devkit/tests/libspid/utests/src/system_utests.c b/cleopatre/devkit/tests/libspid/utests/src/system_utests.c
index 57af71b273..9044ee95ce 100644
--- a/cleopatre/devkit/tests/libspid/utests/src/system_utests.c
+++ b/cleopatre/devkit/tests/libspid/utests/src/system_utests.c
@@ -382,15 +382,15 @@ START_TEST (test_libspid_system_get_nvram)
/* initialize nvram struct */
memset( &nvram, 0x0, sizeof(spidcom_nvram_t) );
strcpy( nvram.magic, SPC300_NVRAM_MAGIC); /* magic number "NVRAM\0\0\0" */
- nvram.pkg_cfg = 0x123; /* SPC300 package configuration register */
- nvram.gpio_0_7_cfg = 0x45; /* SPC300 GPIO 0 to 7 configuration register */
- nvram.gpio_8_15_cfg = 0x6789; /* SPC300 GPIO 8 to 15 configuration register */
- nvram.dram.sdram.config = 0xABC; /* SPC300 SDRAM configuration register */
- nvram.dram.sdram.timing0 = 0x11; /* SPC300 SDRAM timing register 0 */
- nvram.dram.sdram.timing1 = 0x222; /* SPC300 SDRAM timing register 1 */
- nvram.dram.sdram.refresh = 0xdef; /* SPC300 SDRAM refresh register */
- nvram.img_0_offset = 0x140000; /* offset of first image address */
- nvram.nb_images = 2; /* Max Number of Images present in flash */
+ nvram.pkg_cfg = 0x123; /* SPC300 package configuration register */
+ nvram.io.spcpio.gpio_0_7_cfg = 0x45; /* SPC300 GPIO 0 to 7 configuration register */
+ nvram.io.spcpio.gpio_8_15_cfg = 0x6789; /* SPC300 GPIO 8 to 15 configuration register */
+ nvram.dram.sdram.config = 0xABC; /* SPC300 SDRAM configuration register */
+ nvram.dram.sdram.timing0 = 0x11; /* SPC300 SDRAM timing register 0 */
+ nvram.dram.sdram.timing1 = 0x222; /* SPC300 SDRAM timing register 1 */
+ nvram.dram.sdram.refresh = 0xdef; /* SPC300 SDRAM refresh register */
+ nvram.img_0_offset = 0x140000; /* offset of first image address */
+ nvram.nb_images = 2; /* Max Number of Images present in flash */
system("cp " MTD_TST " " LIBSPID_SYSTEM_MTD_PATH);