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authorFisher Cheng2012-11-30 17:41:08 +0800
committerJulien Lacour2013-10-01 11:30:32 +0200
commit1acf0f895c26837099eeaff6455152dd94fa6d53 (patch)
treef841b2c132fff301ef00d74f1e3dd8ae21341db0 /cleopatre/devkit/rt5572drv/MODULE/include/chip
parentca15306cb8a92c9f2abfc816ef5b69545c838d9f (diff)
cleo/devkit: add Ralink RT5572 driver source code, refs #4213
Diffstat (limited to 'cleopatre/devkit/rt5572drv/MODULE/include/chip')
-rw-r--r--cleopatre/devkit/rt5572drv/MODULE/include/chip/chip_id.h67
-rw-r--r--cleopatre/devkit/rt5572drv/MODULE/include/chip/mac_usb.h508
-rw-r--r--cleopatre/devkit/rt5572drv/MODULE/include/chip/rt2870.h19
-rw-r--r--cleopatre/devkit/rt5572drv/MODULE/include/chip/rt28xx.h39
-rw-r--r--cleopatre/devkit/rt5572drv/MODULE/include/chip/rt3070.h64
-rw-r--r--cleopatre/devkit/rt5572drv/MODULE/include/chip/rt30xx.h56
-rw-r--r--cleopatre/devkit/rt5572drv/MODULE/include/chip/rt3370.h67
-rw-r--r--cleopatre/devkit/rt5572drv/MODULE/include/chip/rt33xx.h69
-rw-r--r--cleopatre/devkit/rt5572drv/MODULE/include/chip/rt35xx.h87
-rw-r--r--cleopatre/devkit/rt5572drv/MODULE/include/chip/rt5390.h152
-rw-r--r--cleopatre/devkit/rt5572drv/MODULE/include/chip/rt5592.h93
-rw-r--r--cleopatre/devkit/rt5572drv/MODULE/include/chip/rtmp_mac.h3181
-rw-r--r--cleopatre/devkit/rt5572drv/MODULE/include/chip/rtmp_phy.h646
13 files changed, 5048 insertions, 0 deletions
diff --git a/cleopatre/devkit/rt5572drv/MODULE/include/chip/chip_id.h b/cleopatre/devkit/rt5572drv/MODULE/include/chip/chip_id.h
new file mode 100644
index 0000000000..6748e30def
--- /dev/null
+++ b/cleopatre/devkit/rt5572drv/MODULE/include/chip/chip_id.h
@@ -0,0 +1,67 @@
+/****************************************************************************
+ * Ralink Tech Inc.
+ * 4F, No. 2 Technology 5th Rd.
+ * Science-based Industrial Park
+ * Hsin-chu, Taiwan, R.O.C.
+ * (c) Copyright 2002, Ralink Technology, Inc.
+ *
+ * All rights reserved. Ralink's source code is an unpublished work and the
+ * use of a copyright notice does not imply otherwise. This source code
+ * contains confidential trade secret material of Ralink Tech. Any attemp
+ * or participation in deciphering, decoding, reverse engineering or in any
+ * way altering the source code is stricitly prohibited, unless the prior
+ * written consent of Ralink Technology, Inc. is obtained.
+ ****************************************************************************
+
+ Module Name:
+ chip_id.h
+
+ Abstract:
+
+ Revision History:
+ Who When What
+ --------- ---------- ----------------------------------------------
+ */
+
+#ifndef __CHIP_ID_H__
+#define __CHIP_ID_H__
+
+
+#define NIC_PCI_VENDOR_ID 0x1814
+
+#define NIC2860_PCI_DEVICE_ID 0x0601
+#define NIC2860_PCIe_DEVICE_ID 0x0681
+#define NIC2760_PCI_DEVICE_ID 0x0701 /* 1T/2R Cardbus ??? */
+#define NIC2790_PCIe_DEVICE_ID 0x0781 /* 1T/2R miniCard */
+
+#define VEN_AWT_PCIe_DEVICE_ID 0x1059
+#define VEN_AWT_PCI_VENDOR_ID 0x1A3B
+
+#define EDIMAX_PCI_VENDOR_ID 0x1432
+
+#define NIC3090_PCIe_DEVICE_ID 0x3090 /* 1T/1R miniCard */
+#define NIC3091_PCIe_DEVICE_ID 0x3091 /* 1T/2R miniCard */
+#define NIC3092_PCIe_DEVICE_ID 0x3092 /* 2T/2R miniCard */
+#define NIC3390_PCIe_DEVICE_ID 0x3390 /* 1T/1R miniCard */
+
+#define NIC3062_PCI_DEVICE_ID 0x3062 /* 2T/2R miniCard */
+#define NIC3562_PCI_DEVICE_ID 0x3562 /* 2T/2R miniCard */
+#define NIC3060_PCI_DEVICE_ID 0x3060 /* 1T/1R miniCard */
+
+#define NIC3592_PCIe_DEVICE_ID 0x3592 /* 2T/2R miniCard */
+
+
+#define NIC3593_PCI_OR_PCIe_DEVICE_ID 0x3593
+#define NIC5390_PCIe_DEVICE_ID 0x5390
+#define NIC539F_PCIe_DEVICE_ID 0x539F
+#define NIC5392_PCIe_DEVICE_ID 0x5392
+#define NIC5360_PCI_DEVICE_ID 0x5360
+#define NIC5362_PCI_DEVICE_ID 0x5362
+
+#define NIC5592_PCIe_DEVICE_ID 0x5592
+
+#define NIC3290_PCIe_DEVICE_ID 0x3290
+
+#define DLINK_PCI_VENDOR_ID 0x1186
+
+#endif /* __CHIP_ID_H__ */
diff --git a/cleopatre/devkit/rt5572drv/MODULE/include/chip/mac_usb.h b/cleopatre/devkit/rt5572drv/MODULE/include/chip/mac_usb.h
new file mode 100644
index 0000000000..db67ac8e20
--- /dev/null
+++ b/cleopatre/devkit/rt5572drv/MODULE/include/chip/mac_usb.h
@@ -0,0 +1,508 @@
+/****************************************************************************
+ * Ralink Tech Inc.
+ * 4F, No. 2 Technology 5th Rd.
+ * Science-based Industrial Park
+ * Hsin-chu, Taiwan, R.O.C.
+ * (c) Copyright 2002, Ralink Technology, Inc.
+ *
+ * All rights reserved. Ralink's source code is an unpublished work and the
+ * use of a copyright notice does not imply otherwise. This source code
+ * contains confidential trade secret material of Ralink Tech. Any attemp
+ * or participation in deciphering, decoding, reverse engineering or in any
+ * way altering the source code is stricitly prohibited, unless the prior
+ * written consent of Ralink Technology, Inc. is obtained.
+ ****************************************************************************
+
+ Module Name:
+ mac_usb.h
+
+ Abstract:
+
+ Revision History:
+ Who When What
+ --------- ---------- ----------------------------------------------
+ */
+
+#ifndef __MAC_USB_H__
+#define __MAC_USB_H__
+
+#include "rtmp_type.h"
+#include "chip/rtmp_mac.h"
+#include "chip/rtmp_phy.h"
+#include "rtmp_iface.h"
+#include "rtmp_dot11.h"
+
+
+#define USB_CYC_CFG 0x02a4
+
+/*#define BEACON_RING_SIZE 2 */
+#define MGMTPIPEIDX 0 /* EP6 is highest priority */
+
+/* os abl move */
+/*#define RTMP_PKT_TAIL_PADDING 11 // 3(max 4 byte padding) + 4 (last packet padding) + 4 (MaxBulkOutsize align padding) */
+
+#define fRTMP_ADAPTER_NEED_STOP_TX \
+ (fRTMP_ADAPTER_NIC_NOT_EXIST | fRTMP_ADAPTER_HALT_IN_PROGRESS | \
+ fRTMP_ADAPTER_RESET_IN_PROGRESS | fRTMP_ADAPTER_BULKOUT_RESET | \
+ fRTMP_ADAPTER_RADIO_OFF | fRTMP_ADAPTER_REMOVE_IN_PROGRESS)
+
+/* */
+/* RXINFO appends at the end of each rx packet. */
+/* */
+#define RXINFO_SIZE 4
+#define RT2870_RXDMALEN_FIELD_SIZE 4
+
+#ifdef RT_BIG_ENDIAN
+typedef struct GNU_PACKED _RXINFO_STRUC {
+#ifndef RT5592
+ UINT32 rsv:8
+#else
+ UINT32 IPCHKERR:1; /* IP checksum error */
+ UINT32 TCPCHKERR:1; /* TCP checksum error */
+ UINT32 IPCHKBPS:1; /* IP checksum bypass(hw does not do checksum) */
+ UINT32 TCPCHKBPS:1; /* TCP/UDP checksum bypass(hw does not do checksum) */
+ UINT32 rsv:4;
+#endif
+ UINT32 PlcpSignal:4;
+ UINT32 LastAMSDU:1;
+ UINT32 CipherAlg:1;
+ UINT32 PlcpRssil:1;
+ UINT32 Decrypted:1;
+ UINT32 AMPDU:1; /* To be moved */
+ UINT32 L2PAD:1;
+ UINT32 RSSI:1;
+ UINT32 HTC:1;
+ UINT32 AMSDU:1; /* rx with 802.3 header, not 802.11 header. */
+ UINT32 CipherErr:2; /* 0: decryption okay, 1:ICV error, 2:MIC error, 3:KEY not valid */
+ UINT32 Crc:1; /* 1: CRC error */
+ UINT32 MyBss:1; /* 1: this frame belongs to the same BSSID */
+ UINT32 Bcast:1; /* 1: this is a broadcast frame */
+ UINT32 Mcast:1; /* 1: this is a multicast frame */
+ UINT32 U2M:1; /* 1: this RX frame is unicast to me */
+ UINT32 FRAG:1;
+ UINT32 NULLDATA:1;
+ UINT32 DATA:1;
+ UINT32 BA:1;
+} RXINFO_STRUC, *PRXINFO_STRUC, RT28XX_RXD_STRUC, *PRT28XX_RXD_STRUC;
+#else
+typedef struct GNU_PACKED _RXINFO_STRUC {
+ UINT32 BA:1;
+ UINT32 DATA:1;
+ UINT32 NULLDATA:1;
+ UINT32 FRAG:1;
+ UINT32 U2M:1; /* 1: this RX frame is unicast to me */
+ UINT32 Mcast:1; /* 1: this is a multicast frame */
+ UINT32 Bcast:1; /* 1: this is a broadcast frame */
+ UINT32 MyBss:1; /* 1: this frame belongs to the same BSSID */
+ UINT32 Crc:1; /* 1: CRC error */
+ UINT32 CipherErr:2; /* 0: decryption okay, 1:ICV error, 2:MIC error, 3:KEY not valid */
+ UINT32 AMSDU:1; /* rx with 802.3 header, not 802.11 header. */
+ UINT32 HTC:1;
+ UINT32 RSSI:1;
+ UINT32 L2PAD:1;
+ UINT32 AMPDU:1; /* To be moved */
+ UINT32 Decrypted:1;
+ UINT32 PlcpRssil:1;
+ UINT32 CipherAlg:1;
+ UINT32 LastAMSDU:1;
+ UINT32 PlcpSignal:4;
+#ifdef RT5592
+ UINT32 rsv:4;
+ UINT32 TCPCHKBPS:1; /* TCP/UDP checksum bypass(hw does not do checksum) */
+ UINT32 IPCHKBPS:1; /* IP checksum bypass(hw does not do checksum) */
+ UINT32 TCPCHKERR:1; /* TCP checksum error */
+ UINT32 IPCHKERR:1; /* IP checksum error */
+#else
+ UINT32 rsv:8;
+#endif
+} RXINFO_STRUC, *PRXINFO_STRUC, RT28XX_RXD_STRUC, *PRT28XX_RXD_STRUC;
+#endif
+
+
+/* */
+/* TXINFO */
+/* */
+#define TXINFO_SIZE 4
+
+#ifdef RT_BIG_ENDIAN
+typedef struct _TXINFO_STRUC {
+ /* Word 0 */
+ UINT32 USBDMATxburst:1;/*used ONLY in USB bulk Aggre. Force USB DMA transmit frame from current selected endpoint */
+ UINT32 USBDMANextVLD:1; /*used ONLY in USB bulk Aggregation, NextValid */
+ UINT32 CSO:1; /* Checksum offload */
+ UINT32 USO:1; /* UDP checksum enable */
+#ifndef USB_BULK_BUF_ALIGMENT
+ UINT32 SwUseLastRound:1; /* Software use. */
+
+#else
+ UINT32 bFragLasAlignmentsectiontRound:1;/* Software use */
+#endif /* USB_BULK_BUF_ALIGMENT */
+ UINT32 QSEL:2; /* select on-chip FIFO ID for 2nd-stage output scheduler.0:MGMT, 1:HCCA 2:EDCA */
+ UINT32 WIV:1; /* Wireless Info Valid. 1 if Driver already fill WI, o if DMA needs to copy WI to correctposition */
+ UINT32 TCPOffset:5;
+ UINT32 IPOffset:3; /* FIXME */
+ UINT32 USBDMATxPktLen:16; /*used ONLY in USB bulk Aggregation, Total byte counts of all sub-frame. */
+} TXINFO_STRUC, *PTXINFO_STRUC;
+#else
+typedef struct _TXINFO_STRUC {
+ /* Word 0 */
+ UINT32 USBDMATxPktLen:16; /*used ONLY in USB bulk Aggregation, Total byte counts of all sub-frame. */
+ UINT32 IPOffset:3; /* FIXME */
+ UINT32 TCPOffset:5;
+ UINT32 WIV:1; /* Wireless Info Valid. 1 if Driver already fill WI, o if DMA needs to copy WI to correctposition */
+ UINT32 QSEL:2; /* select on-chip FIFO ID for 2nd-stage output scheduler.0:MGMT, 1:HCCA 2:EDCA */
+#ifndef USB_BULK_BUF_ALIGMENT
+ UINT32 SwUseLastRound:1; /* Software use. */
+#else
+ UINT32 bFragLasAlignmentsectiontRound:1;/* Software use */
+#endif /* USB_BULK_BUF_ALIGMENT */
+ UINT32 USO:1; /* UDP checksum enable */
+ UINT32 CSO:1; /* Checksum offload */
+ UINT32 USBDMANextVLD:1; /*used ONLY in USB bulk Aggregation, NextValid */
+ UINT32 USBDMATxburst:1;/*used ONLY in USB bulk Aggre. Force USB DMA transmit frame from current selected endpoint */
+} TXINFO_STRUC, *PTXINFO_STRUC;
+#endif
+
+
+/* */
+/* Management ring buffer format */
+/* */
+typedef struct _MGMT_STRUC {
+ BOOLEAN Valid;
+ PUCHAR pBuffer;
+ ULONG Length;
+} MGMT_STRUC, *PMGMT_STRUC;
+
+
+/*////////////////////////////////////////////////////////////////////////*/
+/* The TX_BUFFER structure forms the transmitted USB packet to the device */
+/*////////////////////////////////////////////////////////////////////////*/
+typedef struct __TX_BUFFER{
+ union{
+ UCHAR WirelessPacket[TX_BUFFER_NORMSIZE];
+ HEADER_802_11 NullFrame;
+ PSPOLL_FRAME PsPollPacket;
+ RTS_FRAME RTSFrame;
+ }field;
+ UCHAR Aggregation[4]; /*Buffer for save Aggregation size. */
+} TX_BUFFER, *PTX_BUFFER;
+
+typedef struct __HTTX_BUFFER{
+ union{
+ UCHAR WirelessPacket[MAX_TXBULK_SIZE];
+ HEADER_802_11 NullFrame;
+ PSPOLL_FRAME PsPollPacket;
+ RTS_FRAME RTSFrame;
+ }field;
+ UCHAR Aggregation[4]; /*Buffer for save Aggregation size. */
+} HTTX_BUFFER, *PHTTX_BUFFER;
+
+
+#define EDCA_AC0_PIPE 0 /* Bulk EP1 OUT */
+#define EDCA_AC1_PIPE 1 /* Bulk EP2 OUT */
+#define EDCA_AC2_PIPE 2 /* Bulk EP3 OUT */
+#define EDCA_AC3_PIPE 3 /* Bulk EP4 OUT */
+#define HCCA_PIPE 4 /* Bulk EP5 OUT */
+
+/* used to track driver-generated write irps */
+typedef struct _TX_CONTEXT
+{
+ PVOID pAd; /*Initialized in MiniportInitialize */
+ PURB pUrb; /*Initialized in MiniportInitialize */
+ PIRP pIrp; /*used to cancel pending bulk out. */
+ /*Initialized in MiniportInitialize */
+ PTX_BUFFER TransferBuffer; /*Initialized in MiniportInitialize */
+ ULONG BulkOutSize;
+ UCHAR BulkOutPipeId;
+ UCHAR SelfIdx;
+ BOOLEAN InUse;
+ BOOLEAN bWaitingBulkOut; /* at least one packet is in this TxContext, ready for making IRP anytime. */
+ BOOLEAN bFullForBulkOut; /* all tx buffer are full , so waiting for tx bulkout. */
+ BOOLEAN IRPPending;
+ BOOLEAN LastOne;
+ BOOLEAN bAggregatible;
+ UCHAR Header_802_3[LENGTH_802_3];
+ UCHAR Rsv[2];
+ ULONG DataOffset;
+ UINT TxRate;
+ ra_dma_addr_t data_dma;
+
+#ifdef UAPSD_SUPPORT
+ USHORT Wcid;
+#endif /* UAPSD_SUPPORT */
+} TX_CONTEXT, *PTX_CONTEXT, **PPTX_CONTEXT;
+
+
+/* used to track driver-generated write irps */
+typedef struct _HT_TX_CONTEXT
+{
+ PVOID pAd; /*Initialized in MiniportInitialize */
+ PURB pUrb; /*Initialized in MiniportInitialize */
+ PIRP pIrp; /*used to cancel pending bulk out. */
+ /*Initialized in MiniportInitialize */
+ PHTTX_BUFFER TransferBuffer; /*Initialized in MiniportInitialize */
+ ULONG BulkOutSize; /* Indicate the total bulk-out size in bytes in one bulk-transmission */
+ UCHAR BulkOutPipeId;
+ BOOLEAN IRPPending;
+ BOOLEAN LastOne;
+ BOOLEAN bCurWriting;
+ BOOLEAN bRingEmpty;
+ BOOLEAN bCopySavePad;
+ UCHAR SavedPad[8];
+ UCHAR Header_802_3[LENGTH_802_3];
+ ULONG CurWritePosition; /* Indicate the buffer offset which packet will be inserted start from. */
+ ULONG CurWriteRealPos; /* Indicate the buffer offset which packet now are writing to. */
+ ULONG NextBulkOutPosition; /* Indicate the buffer start offset of a bulk-transmission */
+ ULONG ENextBulkOutPosition; /* Indicate the buffer end offset of a bulk-transmission */
+ UINT TxRate;
+ ra_dma_addr_t data_dma; /* urb dma on linux */
+#ifdef USB_BULK_BUF_ALIGMENT
+ ULONG CurWriteIdx; /* pointer to next 32k bytes position when wirte tx resource or when bulk out sizze not > 0x6000 */
+ ULONG NextBulkIdx; /* pointer to next alignment section when bulk ot */
+#endif /* USB_BULK_BUF_ALIGMENT */
+
+} HT_TX_CONTEXT, *PHT_TX_CONTEXT, **PPHT_TX_CONTEXT;
+
+
+/* */
+/* Structure to keep track of receive packets and buffers to indicate */
+/* receive data to the protocol. */
+/* */
+typedef struct _RX_CONTEXT
+{
+ PUCHAR TransferBuffer;
+ PVOID pAd;
+ PIRP pIrp;/*used to cancel pending bulk in. */
+ PURB pUrb;
+ /*These 2 Boolean shouldn't both be 1 at the same time. */
+ ULONG BulkInOffset; /* number of packets waiting for reordering . */
+/* BOOLEAN ReorderInUse; // At least one packet in this buffer are in reordering buffer and wait for receive indication */
+ BOOLEAN bRxHandling; /* Notify this packet is being process now. */
+ BOOLEAN InUse; /* USB Hardware Occupied. Wait for USB HW to put packet. */
+ BOOLEAN Readable; /* Receive Complete back. OK for driver to indicate receiving packet. */
+ BOOLEAN IRPPending; /* TODO: To be removed */
+ /*atomic_t IrpLock; */
+ NDIS_SPIN_LOCK RxContextLock;
+ ra_dma_addr_t data_dma; /* urb dma on linux */
+} RX_CONTEXT, *PRX_CONTEXT;
+
+
+/******************************************************************************
+
+ USB Frimware Related MACRO
+
+******************************************************************************/
+/* 8051 firmware image for usb - use last-half base address = 0x3000 */
+#define FIRMWARE_IMAGE_BASE 0x3000
+#define MAX_FIRMWARE_IMAGE_SIZE 0x1000 /* 4kbyte */
+
+#define RTMP_WRITE_FIRMWARE(_pAd, _pFwImage, _FwLen) \
+ RTUSBFirmwareWrite(_pAd, _pFwImage, _FwLen)
+
+
+
+/******************************************************************************
+
+ USB TX Related MACRO
+
+******************************************************************************/
+#define RTMP_START_DEQUEUE(pAd, QueIdx, irqFlags) \
+ { \
+ RTMP_IRQ_LOCK(&pAd->DeQueueLock[QueIdx], irqFlags); \
+ if (pAd->DeQueueRunning[QueIdx]) \
+ { \
+ RTMP_IRQ_UNLOCK(&pAd->DeQueueLock[QueIdx], irqFlags);\
+ DBGPRINT(RT_DEBUG_OFF, ("DeQueueRunning[%d]= TRUE!\n", QueIdx)); \
+ continue; \
+ } \
+ else \
+ { \
+ pAd->DeQueueRunning[QueIdx] = TRUE; \
+ RTMP_IRQ_UNLOCK(&pAd->DeQueueLock[QueIdx], irqFlags);\
+ } \
+ }
+
+#define RTMP_STOP_DEQUEUE(pAd, QueIdx, irqFlags) \
+ do{ \
+ RTMP_IRQ_LOCK(&pAd->DeQueueLock[QueIdx], irqFlags); \
+ pAd->DeQueueRunning[QueIdx] = FALSE; \
+ RTMP_IRQ_UNLOCK(&pAd->DeQueueLock[QueIdx], irqFlags); \
+ }while(0)
+
+#define RTMP_HAS_ENOUGH_FREE_DESC(pAd, pTxBlk, freeNum, pPacket) \
+ (RTUSBFreeDescriptorRequest(pAd, pTxBlk->QueIdx, (pTxBlk->TotalFrameLen + GET_OS_PKT_LEN(pPacket))) == NDIS_STATUS_SUCCESS)
+
+#define RTMP_RELEASE_DESC_RESOURCE(pAd, QueIdx) \
+ do{}while(0)
+
+#define NEED_QUEUE_BACK_FOR_AGG(_pAd, _QueIdx, _freeNum, _TxFrameType) \
+ ((_TxFrameType == TX_RALINK_FRAME) && (RTUSBNeedQueueBackForAgg(_pAd, _QueIdx)))
+
+#define HAL_WriteSubTxResource(pAd, pTxBlk, bIsLast, pFreeNumber) \
+ RtmpUSB_WriteSubTxResource(pAd, pTxBlk, bIsLast, pFreeNumber)
+
+#define HAL_WriteTxResource(pAd, pTxBlk,bIsLast, pFreeNumber) \
+ RtmpUSB_WriteSingleTxResource(pAd, pTxBlk,bIsLast, pFreeNumber)
+
+#define HAL_WriteFragTxResource(pAd, pTxBlk, fragNum, pFreeNumber) \
+ RtmpUSB_WriteFragTxResource(pAd, pTxBlk, fragNum, pFreeNumber)
+
+#define HAL_WriteMultiTxResource(pAd, pTxBlk,frameNum, pFreeNumber) \
+ RtmpUSB_WriteMultiTxResource(pAd, pTxBlk,frameNum, pFreeNumber)
+
+#define HAL_FinalWriteTxResource(pAd, pTxBlk, totalMPDUSize, TxIdx) \
+ RtmpUSB_FinalWriteTxResource(pAd, pTxBlk, totalMPDUSize, TxIdx)
+
+#define HAL_LastTxIdx(pAd, QueIdx,TxIdx) \
+ /*RtmpUSBDataLastTxIdx(pAd, QueIdx,TxIdx)*/
+
+#define HAL_KickOutTx(pAd, pTxBlk, QueIdx) \
+ RtmpUSBDataKickOut(pAd, pTxBlk, QueIdx)
+
+#define HAL_KickOutMgmtTx(pAd, QueIdx, pPacket, pSrcBufVA, SrcBufLen) \
+ RtmpUSBMgmtKickOut(pAd, QueIdx, pPacket, pSrcBufVA, SrcBufLen)
+
+#define HAL_KickOutNullFrameTx(_pAd, _QueIdx, _pNullFrame, _frameLen) \
+ RtmpUSBNullFrameKickOut(_pAd, _QueIdx, _pNullFrame, _frameLen)
+
+#define GET_TXRING_FREENO(_pAd, _QueIdx) (_QueIdx) /*(_pAd->TxRing[_QueIdx].TxSwFreeIdx) */
+#define GET_MGMTRING_FREENO(_pAd) (_pAd->MgmtRing.TxSwFreeIdx)
+
+
+/* ----------------- RX Related MACRO ----------------- */
+
+
+/*
+ * Device Hardware Interface Related MACRO
+ */
+#define RTMP_IRQ_INIT(pAd) do{}while(0)
+#define RTMP_IRQ_ENABLE(pAd) do{}while(0)
+
+
+/*
+ * MLME Related MACRO
+ */
+#define RTMP_MLME_HANDLER(pAd) RTUSBMlmeUp(&(pAd->mlmeTask))
+
+#define RTMP_MLME_PRE_SANITY_CHECK(pAd) \
+ { if ((pAd->StaCfg.bHardwareRadio == TRUE) && \
+ (!RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_NIC_NOT_EXIST)) && \
+ (!RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_HALT_IN_PROGRESS))) { \
+ RTEnqueueInternalCmd(pAd, CMDTHREAD_CHECK_GPIO, NULL, 0); } }
+
+#define RTMP_MLME_RESET_STATE_MACHINE(pAd) \
+ MlmeEnqueue(pAd, MLME_CNTL_STATE_MACHINE, MT2_RESET_CONF, 0, NULL, 0); \
+ RTUSBMlmeUp(&(pAd->mlmeTask));
+
+#define RTMP_HANDLE_COUNTER_MEASURE(_pAd, _pEntry) \
+ { RTEnqueueInternalCmd(_pAd, CMDTHREAD_802_11_COUNTER_MEASURE, _pEntry, sizeof(MAC_TABLE_ENTRY)); \
+ RTUSBMlmeUp(&(_pAd->mlmeTask)); \
+ }
+
+
+/*
+ * Power Save Related MACRO
+ */
+
+#define RTMP_MLME_RADIO_ON(pAd) \
+ RT28xxUsbMlmeRadioOn(pAd);
+
+#define RTMP_MLME_RADIO_OFF(pAd) \
+ RT28xxUsbMlmeRadioOFF(pAd);
+
+/* MAC Search table */
+/* add this entry into ASIC RX WCID search table */
+#define RTMP_STA_ENTRY_ADD(pAd, pEntry) \
+{ \
+ RT_SET_ASIC_WCID Info; \
+ \
+ Info.WCID = pEntry->Aid; \
+ NdisMoveMemory(Info.Addr, pEntry->Addr, MAC_ADDR_LEN); \
+ \
+ RTEnqueueInternalCmd(pAd, CMDTHREAD_SET_CLIENT_MAC_ENTRY, \
+ &Info, sizeof(RT_SET_ASIC_WCID)); \
+}
+
+/* ----------------- Security Related MACRO ----------------- */
+
+/* Set Asic WCID Attribute table */
+#define RTMP_SET_WCID_SEC_INFO(_pAd, _BssIdx, _KeyIdx, _CipherAlg, _Wcid, _KeyTabFlag) \
+{ \
+ RT_ASIC_WCID_SEC_INFO Info; \
+ \
+ Info.BssIdx = _BssIdx; \
+ Info.KeyIdx = _KeyIdx; \
+ Info.CipherAlg = _CipherAlg; \
+ Info.Wcid = _Wcid; \
+ Info.KeyTabFlag = _KeyTabFlag; \
+ \
+ RTEnqueueInternalCmd(_pAd, CMDTHREAD_SET_WCID_SEC_INFO, \
+ &Info, sizeof(RT_ASIC_WCID_SEC_INFO)); \
+}
+
+/* Set Asic WCID IV/EIV table */
+#define RTMP_ASIC_WCID_IVEIV_TABLE(_pAd, _Wcid, _uIV, _uEIV) \
+{ \
+ RT_ASIC_WCID_IVEIV_ENTRY Info; \
+ \
+ Info.Wcid = _Wcid; \
+ Info.Iv = _uIV; \
+ Info.Eiv = _uEIV; \
+ \
+ RTEnqueueInternalCmd(_pAd, CMDTHREAD_SET_ASIC_WCID_IVEIV, \
+ &Info, \
+ sizeof(RT_ASIC_WCID_IVEIV_ENTRY)); \
+}
+
+/* Set Asic WCID Attribute table */
+#define RTMP_ASIC_WCID_ATTR_TABLE(_pAd, _BssIdx, _KeyIdx, _CipherAlg, _Wcid, _KeyTabFlag) \
+{ \
+ RT_ASIC_WCID_ATTR_ENTRY Info; \
+ \
+ Info.BssIdx = _BssIdx; \
+ Info.KeyIdx = _KeyIdx; \
+ Info.CipherAlg = _CipherAlg; \
+ Info.Wcid = _Wcid; \
+ Info.KeyTabFlag = _KeyTabFlag; \
+ \
+ RTEnqueueInternalCmd(_pAd, CMDTHREAD_SET_ASIC_WCID_ATTR, \
+ &Info, sizeof(RT_ASIC_WCID_ATTR_ENTRY)); \
+}
+
+/* Set Asic Pairwise key table */
+#define RTMP_ASIC_PAIRWISE_KEY_TABLE(_pAd, _WCID, _pCipherKey) \
+{ \
+ RT_ASIC_PAIRWISE_KEY Info; \
+ \
+ Info.WCID = _WCID; \
+ NdisMoveMemory(&Info.CipherKey, _pCipherKey, sizeof(CIPHER_KEY)); \
+ \
+ RTEnqueueInternalCmd(_pAd, CMDTHREAD_SET_ASIC_PAIRWISE_KEY, \
+ &Info, sizeof(RT_ASIC_PAIRWISE_KEY)); \
+}
+
+/* Set Asic Shared key table */
+#define RTMP_ASIC_SHARED_KEY_TABLE(_pAd, _BssIndex, _KeyIdx, _pCipherKey) \
+{ \
+ RT_ASIC_SHARED_KEY Info; \
+ \
+ Info.BssIndex = _BssIndex; \
+ Info.KeyIdx = _KeyIdx; \
+ NdisMoveMemory(&Info.CipherKey, _pCipherKey, sizeof(CIPHER_KEY)); \
+ \
+ RTEnqueueInternalCmd(_pAd, CMDTHREAD_SET_ASIC_SHARED_KEY, \
+ &Info, sizeof(RT_ASIC_SHARED_KEY)); \
+}
+
+
+/* Remove Pairwise Key table */
+#define RTMP_REMOVE_PAIRWISE_KEY_ENTRY(_pAd, _Wcid) \
+{ \
+ UCHAR _tWcid =_Wcid; \
+ RTEnqueueInternalCmd(_pAd, CMDTHREAD_REMOVE_PAIRWISE_KEY, &(_tWcid), sizeof(UCHAR));\
+}
+
+#define RTMP_OS_IRQ_RELEASE(_pAd, _NetDev)
+
+#endif /*__MAC_USB_H__ */
+
diff --git a/cleopatre/devkit/rt5572drv/MODULE/include/chip/rt2870.h b/cleopatre/devkit/rt5572drv/MODULE/include/chip/rt2870.h
new file mode 100644
index 0000000000..6c3caa192d
--- /dev/null
+++ b/cleopatre/devkit/rt5572drv/MODULE/include/chip/rt2870.h
@@ -0,0 +1,19 @@
+
+#ifndef __RT2870_H__
+#define __RT2870_H__
+
+#ifdef RT2870
+
+#ifndef RTMP_USB_SUPPORT
+#error "For RT2870, you should define the compile flag -DRTMP_USB_SUPPORT"
+#endif
+
+#ifndef RTMP_MAC_USB
+#error "For RT2870, you should define the compile flag -DRTMP_MAC_USB"
+#endif
+
+#include "rtmp_type.h"
+
+#endif /* RT2870 */
+#endif /*__RT2870_H__ */
+
diff --git a/cleopatre/devkit/rt5572drv/MODULE/include/chip/rt28xx.h b/cleopatre/devkit/rt5572drv/MODULE/include/chip/rt28xx.h
new file mode 100644
index 0000000000..3eacae6497
--- /dev/null
+++ b/cleopatre/devkit/rt5572drv/MODULE/include/chip/rt28xx.h
@@ -0,0 +1,39 @@
+/****************************************************************************
+ * Ralink Tech Inc.
+ * 4F, No. 2 Technology 5th Rd.
+ * Science-based Industrial Park
+ * Hsin-chu, Taiwan, R.O.C.
+ * (c) Copyright 2002, Ralink Technology, Inc.
+ *
+ * All rights reserved. Ralink's source code is an unpublished work and the
+ * use of a copyright notice does not imply otherwise. This source code
+ * contains confidential trade secret material of Ralink Tech. Any attemp
+ * or participation in deciphering, decoding, reverse engineering or in any
+ * way altering the source code is stricitly prohibited, unless the prior
+ * written consent of Ralink Technology, Inc. is obtained.
+ ****************************************************************************
+
+ Module Name:
+ rt28xx.h
+
+ Abstract:
+
+ Revision History:
+ Who When What
+ --------- ---------- ----------------------------------------------
+ */
+
+#ifndef __RT28XX_H__
+#define __RT28XX_H__
+
+#ifdef RT28xx
+
+VOID RT28xx_ChipSwitchChannel(
+ IN struct _RTMP_ADAPTER *pAd,
+ IN UCHAR Channel,
+ IN BOOLEAN bScan);
+
+#endif /* RT28xx */
+
+#endif /*__RT28XX_H__ */
+
diff --git a/cleopatre/devkit/rt5572drv/MODULE/include/chip/rt3070.h b/cleopatre/devkit/rt5572drv/MODULE/include/chip/rt3070.h
new file mode 100644
index 0000000000..e70419bbaf
--- /dev/null
+++ b/cleopatre/devkit/rt5572drv/MODULE/include/chip/rt3070.h
@@ -0,0 +1,64 @@
+/****************************************************************************
+ * Ralink Tech Inc.
+ * 4F, No. 2 Technology 5th Rd.
+ * Science-based Industrial Park
+ * Hsin-chu, Taiwan, R.O.C.
+ * (c) Copyright 2002, Ralink Technology, Inc.
+ *
+ * All rights reserved. Ralink's source code is an unpublished work and the
+ * use of a copyright notice does not imply otherwise. This source code
+ * contains confidential trade secret material of Ralink Tech. Any attemp
+ * or participation in deciphering, decoding, reverse engineering or in any
+ * way altering the source code is stricitly prohibited, unless the prior
+ * written consent of Ralink Technology, Inc. is obtained.
+ ****************************************************************************
+
+ Module Name:
+ rt3070.h
+
+ Abstract:
+
+ Revision History:
+ Who When What
+ --------- ---------- ----------------------------------------------
+ */
+
+#ifndef __RT3070_H__
+#define __RT3070_H__
+
+#ifdef RT3070
+
+struct _RTMP_ADAPTER;
+struct _RSSI_SAMPLE;
+
+#ifndef RTMP_USB_SUPPORT
+#error "For RT3070, you should define the compile flag -DRTMP_USB_SUPPORT"
+#endif
+
+#ifndef RTMP_MAC_USB
+#error "For RT3070, you should define the compile flag -DRTMP_MAC_USB"
+#endif
+
+#ifndef RTMP_RF_RW_SUPPORT
+#error "For RT3070, you should define the compile flag -DRTMP_RF_RW_SUPPORT"
+#endif
+
+#ifndef RT30xx
+#error "For RT3070, you should define the compile flag -DRT30xx"
+#endif
+
+#include "chip/rt30xx.h"
+
+/*
+ Device ID & Vendor ID, these values should match EEPROM value
+*/
+
+
+VOID RT3070_PowerTuning(
+ IN struct _RTMP_ADAPTER *pAd,
+ IN struct _RSSI_SAMPLE *pRssi);
+
+#endif /* RT3070 */
+
+#endif /* __RT3070_H__ */
+
diff --git a/cleopatre/devkit/rt5572drv/MODULE/include/chip/rt30xx.h b/cleopatre/devkit/rt5572drv/MODULE/include/chip/rt30xx.h
new file mode 100644
index 0000000000..af84801a25
--- /dev/null
+++ b/cleopatre/devkit/rt5572drv/MODULE/include/chip/rt30xx.h
@@ -0,0 +1,56 @@
+/****************************************************************************
+ * Ralink Tech Inc.
+ * 4F, No. 2 Technology 5th Rd.
+ * Science-based Industrial Park
+ * Hsin-chu, Taiwan, R.O.C.
+ * (c) Copyright 2002, Ralink Technology, Inc.
+ *
+ * All rights reserved. Ralink's source code is an unpublished work and the
+ * use of a copyright notice does not imply otherwise. This source code
+ * contains confidential trade secret material of Ralink Tech. Any attemp
+ * or participation in deciphering, decoding, reverse engineering or in any
+ * way altering the source code is stricitly prohibited, unless the prior
+ * written consent of Ralink Technology, Inc. is obtained.
+ ****************************************************************************
+
+ Module Name:
+ rt30xx.h
+
+ Abstract:
+
+ Revision History:
+ Who When What
+ --------- ---------- ----------------------------------------------
+ */
+
+#ifndef __RT30XX_H__
+#define __RT30XX_H__
+
+#ifdef RT30xx
+
+struct _RTMP_ADAPTER;
+
+#include "rtmp_type.h"
+
+extern REG_PAIR RT3020_RFRegTable[];
+extern UCHAR NUM_RF_3020_REG_PARMS;
+
+VOID RT30xx_Init(
+ IN struct _RTMP_ADAPTER *pAd);
+
+VOID RT30xx_ChipSwitchChannel(
+ IN struct _RTMP_ADAPTER *pAd,
+ IN UCHAR Channel,
+ IN BOOLEAN bScan);
+
+VOID RT30xx_ChipBBPAdjust(
+ IN struct _RTMP_ADAPTER *pAd);
+
+VOID RT30xx_ChipAGCInit(
+ IN struct _RTMP_ADAPTER *pAd,
+ IN UCHAR BandWidth);
+
+#endif /* RT30xx */
+
+#endif /*__RT30XX_H__ */
+
diff --git a/cleopatre/devkit/rt5572drv/MODULE/include/chip/rt3370.h b/cleopatre/devkit/rt5572drv/MODULE/include/chip/rt3370.h
new file mode 100644
index 0000000000..59c3ce9993
--- /dev/null
+++ b/cleopatre/devkit/rt5572drv/MODULE/include/chip/rt3370.h
@@ -0,0 +1,67 @@
+/****************************************************************************
+ * Ralink Tech Inc.
+ * 4F, No. 2 Technology 5th Rd.
+ * Science-based Industrial Park
+ * Hsin-chu, Taiwan, R.O.C.
+ * (c) Copyright 2002, Ralink Technology, Inc.
+ *
+ * All rights reserved. Ralink's source code is an unpublished work and the
+ * use of a copyright notice does not imply otherwise. This source code
+ * contains confidential trade secret material of Ralink Tech. Any attemp
+ * or participation in deciphering, decoding, reverse engineering or in any
+ * way altering the source code is stricitly prohibited, unless the prior
+ * written consent of Ralink Technology, Inc. is obtained.
+ ****************************************************************************
+
+ Module Name:
+ rt3070.h
+
+ Abstract:
+
+ Revision History:
+ Who When What
+ --------- ---------- ----------------------------------------------
+ */
+
+#ifndef __RT3370_H__
+#define __RT3370_H__
+
+#ifdef RT3370
+
+
+#ifndef RTMP_USB_SUPPORT
+#error "For RT3070, you should define the compile flag -DRTMP_USB_SUPPORT"
+#endif
+
+#ifndef RTMP_MAC_USB
+#error "For RT3070, you should define the compile flag -DRTMP_MAC_USB"
+#endif
+
+#ifndef RTMP_RF_RW_SUPPORT
+#error "For RT3070, you should define the compile flag -DRTMP_RF_RW_SUPPORT"
+#endif
+
+#ifndef RT33xx
+#error "For RT3370, you should define the compile flag -DRT33xx"
+#endif
+
+#ifndef RT30xx
+#error "For RT3070, you should define the compile flag -DRT30xx"
+#endif
+
+
+#include "chip/rt30xx.h"
+#include "chip/rt33xx.h"
+
+extern REG_PAIR RT3370_BBPRegTable[];
+extern UCHAR RT3370_NUM_BBP_REG_PARMS;
+
+
+/* */
+/* Device ID & Vendor ID, these values should match EEPROM value */
+/* */
+
+#endif /* RT3370 */
+
+#endif /*__RT3370_H__ */
+
diff --git a/cleopatre/devkit/rt5572drv/MODULE/include/chip/rt33xx.h b/cleopatre/devkit/rt5572drv/MODULE/include/chip/rt33xx.h
new file mode 100644
index 0000000000..569bf951aa
--- /dev/null
+++ b/cleopatre/devkit/rt5572drv/MODULE/include/chip/rt33xx.h
@@ -0,0 +1,69 @@
+/****************************************************************************
+ * Ralink Tech Inc.
+ * 4F, No. 2 Technology 5th Rd.
+ * Science-based Industrial Park
+ * Hsin-chu, Taiwan, R.O.C.
+ * (c) Copyright 2002, Ralink Technology, Inc.
+ *
+ * All rights reserved. Ralink's source code is an unpublished work and the
+ * use of a copyright notice does not imply otherwise. This source code
+ * contains confidential trade secret material of Ralink Tech. Any attemp
+ * or participation in deciphering, decoding, reverse engineering or in any
+ * way altering the source code is stricitly prohibited, unless the prior
+ * written consent of Ralink Technology, Inc. is obtained.
+ ****************************************************************************
+
+ Module Name:
+ rt30xx.h
+
+ Abstract:
+
+ Revision History:
+ Who When What
+ --------- ---------- ----------------------------------------------
+ */
+
+#ifndef __RT33XX_H__
+#define __RT33XX_H__
+
+#ifdef RT33xx
+
+#include "rtmp_type.h"
+
+
+#ifdef RT3370
+extern REG_PAIR RT3370_RFRegTable[];
+extern UCHAR RT3370_NUM_RF_REG_PARMS;
+#define BW20RFR24 0x4F
+#define BW40RFR24 0X68
+#define BW20RFR31 0x4F
+#define BW40RFR31 0X6F
+#endif /* RT3370 */
+
+VOID RT33xx_Init(
+ IN struct _RTMP_ADAPTER *pAd);
+
+VOID RT33xx_ChipSwitchChannel(
+ IN struct _RTMP_ADAPTER *pAd,
+ IN UCHAR Channel,
+ IN BOOLEAN bScan);
+
+#ifdef RTMP_INTERNAL_TX_ALC
+VOID RT33xx_InitDesiredTSSITable(
+ IN struct _RTMP_ADAPTER *pAd);
+
+UCHAR RT33xx_GetDesiredTSSI(
+ IN struct _RTMP_ADAPTER *pAd);
+
+VOID RT33xx_AsicTxAlcGetAutoAgcOffset(
+ IN struct _RTMP_ADAPTER *pAd,
+ IN PCHAR pDeltaPwr,
+ IN PCHAR pTotalDeltaPwr,
+ IN PCHAR pAgcCompensate,
+ IN PCHAR pDeltaPowerByBbpR1);
+#endif /* RTMP_INTERNAL_TX_ALC */
+
+#endif /* RT33xx */
+
+#endif /*__RT33XX_H__ */
+
diff --git a/cleopatre/devkit/rt5572drv/MODULE/include/chip/rt35xx.h b/cleopatre/devkit/rt5572drv/MODULE/include/chip/rt35xx.h
new file mode 100644
index 0000000000..fd5e998548
--- /dev/null
+++ b/cleopatre/devkit/rt5572drv/MODULE/include/chip/rt35xx.h
@@ -0,0 +1,87 @@
+/****************************************************************************
+ * Ralink Tech Inc.
+ * 4F, No. 2 Technology 5th Rd.
+ * Science-based Industrial Park
+ * Hsin-chu, Taiwan, R.O.C.
+ * (c) Copyright 2002, Ralink Technology, Inc.
+ *
+ * All rights reserved. Ralink's source code is an unpublished work and the
+ * use of a copyright notice does not imply otherwise. This source code
+ * contains confidential trade secret material of Ralink Tech. Any attemp
+ * or participation in deciphering, decoding, reverse engineering or in any
+ * way altering the source code is stricitly prohibited, unless the prior
+ * written consent of Ralink Technology, Inc. is obtained.
+ ****************************************************************************
+
+ Module Name:
+ rt35xx.h
+
+ Abstract:
+
+ Revision History:
+ Who When What
+ --------- ---------- ----------------------------------------------
+ */
+
+#ifndef __RT35XX_H__
+#define __RT35XX_H__
+
+#ifdef RT35xx
+
+struct _RTMP_ADAPTER;
+
+#ifndef RTMP_RF_RW_SUPPORT
+#error "For RT3062/3562/3572/3592, you should define the compile flag -DRTMP_RF_RW_SUPPORT"
+#endif
+
+#include "chip/rt30xx.h"
+
+extern REG_PAIR RF3572_RFRegTable[];
+
+/* */
+/* Device ID & Vendor ID, these values should match EEPROM value */
+/* */
+#define NIC3062_PCI_DEVICE_ID 0x3062 /* 2T/2R miniCard */
+#define NIC3562_PCI_DEVICE_ID 0x3562 /* 2T/2R miniCard */
+#define NIC3060_PCI_DEVICE_ID 0x3060 /* 1T/1R miniCard */
+
+#define EDIMAX_PCI_VENDOR_ID 0x1432
+
+/* use CHIPSET = 3562 compile */
+#define NIC3592_PCIe_DEVICE_ID 0x3592 /* 2T/2R miniCard */
+
+VOID RT35xx_Init(
+ IN struct _RTMP_ADAPTER *pAd);
+
+VOID NICInitRT35xxMacRegisters(
+ IN struct _RTMP_ADAPTER *pAd);
+
+VOID RT35xx_ChipSwitchChannel(
+ IN struct _RTMP_ADAPTER *pAd,
+ IN UCHAR Channel,
+ IN BOOLEAN bScan);
+
+VOID RT35xx_RxSensitivityTuning(
+ IN struct _RTMP_ADAPTER *pAd);
+
+VOID NICInitRT3572RFRegisters(
+ IN struct _RTMP_ADAPTER *pAd);
+
+VOID RT3572ReverseRFSleepModeSetup(
+ IN struct _RTMP_ADAPTER *pAd,
+ IN BOOLEAN FlgIsInitState);
+
+VOID RT35xx_NICInitAsicFromEEPROM(
+ IN struct _RTMP_ADAPTER *pAd);
+
+UCHAR RT35xx_ChipAGCAdjust(
+ IN struct _RTMP_ADAPTER *pAd,
+ IN CHAR Rssi,
+ IN UCHAR R66);
+
+VOID RT35xx_ChipBBPAdjust(
+ IN struct _RTMP_ADAPTER *pAd);
+
+#endif /* RT35xx */
+#endif /*__RT35XX_H__ */
+
diff --git a/cleopatre/devkit/rt5572drv/MODULE/include/chip/rt5390.h b/cleopatre/devkit/rt5572drv/MODULE/include/chip/rt5390.h
new file mode 100644
index 0000000000..6d77757a45
--- /dev/null
+++ b/cleopatre/devkit/rt5572drv/MODULE/include/chip/rt5390.h
@@ -0,0 +1,152 @@
+/****************************************************************************
+ * Ralink Tech Inc.
+ * 4F, No. 2 Technology 5th Rd.
+ * Science-based Industrial Park
+ * Hsin-chu, Taiwan, R.O.C.
+ * (c) Copyright 2002, Ralink Technology, Inc.
+ *
+ * All rights reserved. Ralink's source code is an unpublished work and the
+ * use of a copyright notice does not imply otherwise. This source code
+ * contains confidential trade secret material of Ralink Tech. Any attemp
+ * or participation in deciphering, decoding, reverse engineering or in any
+ * way altering the source code is stricitly prohibited, unless the prior
+ * written consent of Ralink Technology, Inc. is obtained.
+ ****************************************************************************
+
+ Module Name:
+ rt5390.h
+
+ Abstract:
+
+ Revision History:
+ Who When What
+ --------- ---------- ----------------------------------------------
+ */
+
+#ifndef __RT5390_H__
+#define __RT5390_H__
+
+#if defined(RT5370) || defined(RT5372) || defined(RT5390) || defined(RT5392)
+
+#ifndef RTMP_RF_RW_SUPPORT
+#error "For RT5390, you should define the compile flag -DRTMP_RF_RW_SUPPORT"
+#endif
+
+#ifndef RT30xx
+#error "For RT5390, you should define the compile flag -DRT30xx"
+#endif
+
+#include "chip/rt30xx.h"
+
+extern REG_PAIR RF5390RegTable[];
+extern UCHAR NUM_RF_5390_REG_PARMS;
+
+
+#define BBP_REG_BF BBP_R163 /* TxBf control */
+
+#ifdef RTMP_FLASH_SUPPORT
+#define EEPROM_DEFAULT_FILE_PATH "/etc_ro/Wireless/iNIC/RT5392_PCIe_2T2R_ALC_V1_3.bin"
+#define RF_OFFSET 0x48000
+#endif /* RTMP_FLASH_SUPPORT */
+
+/* Device ID & Vendor ID, these values should match EEPROM value */
+#define NIC5390_PCIe_DEVICE_ID 0x5390
+#define NIC539F_PCIe_DEVICE_ID 0x539F
+#define NIC5392_PCIe_DEVICE_ID 0x5392
+#define NIC5360_PCI_DEVICE_ID 0x5360
+#define NIC5362_PCI_DEVICE_ID 0x5362
+
+VOID RT5390HaltAction(
+ IN struct _RTMP_ADAPTER *pAd);
+
+VOID RT5390LoadRFNormalModeSetup(
+ IN struct _RTMP_ADAPTER *pAd);
+
+VOID RT5390LoadRFSleepModeSetup(
+ IN struct _RTMP_ADAPTER *pAd);
+
+VOID RT5390ReverseRFSleepModeSetup(
+ IN struct _RTMP_ADAPTER *pAd,
+ IN BOOLEAN FlgIsInitState);
+
+VOID RT5390_Init(
+ IN struct _RTMP_ADAPTER *pAd);
+
+VOID NICInitRT5390BbpRegisters(
+ IN struct _RTMP_ADAPTER *pAd);
+
+VOID NICInitRT5390MacRegisters(
+ IN struct _RTMP_ADAPTER *pAd);
+
+VOID NICInitRT5392MacRegisters(
+ IN struct _RTMP_ADAPTER *pAd);
+
+VOID RT5390_RxSensitivityTuning(
+ IN struct _RTMP_ADAPTER *pAd);
+
+UCHAR RT5390_ChipAGCAdjust(
+ IN struct _RTMP_ADAPTER *pAd,
+ IN CHAR Rssi,
+ IN UCHAR OrigR66Value);
+
+VOID RT5390_ChipBBPAdjust(
+ IN struct _RTMP_ADAPTER *pAd);
+
+VOID RT5390_ChipSwitchChannel(
+ IN struct _RTMP_ADAPTER *pAd,
+ IN UCHAR Channel,
+ IN BOOLEAN bScan);
+
+VOID RT539x_AsicExtraPowerOverMAC(
+ IN struct _RTMP_ADAPTER *pAd);
+
+#ifdef RTMP_INTERNAL_TX_ALC
+
+VOID RT5390_InitDesiredTSSITable(
+ IN struct _RTMP_ADAPTER *pAd);
+
+INT RT5390_ATETssiCalibration(
+ IN struct _RTMP_ADAPTER *pAd,
+ IN PSTRING arg);
+
+INT RT5390_ATETssiCalibrationExtend(
+ IN struct _RTMP_ADAPTER *pAd,
+ IN PSTRING arg);
+
+VOID RT5390_AsicTxAlcGetAutoAgcOffset(
+ IN struct _RTMP_ADAPTER *pAd,
+ IN PCHAR pDeltaPwr,
+ IN PCHAR pTotalDeltaPwr,
+ IN PCHAR pAgcCompensate,
+ IN PCHAR pDeltaPowerByBbpR1);
+
+LONG Rounding(
+ IN struct _RTMP_ADAPTER *pAd,
+ IN LONG Integer,
+ IN LONG Fraction,
+ IN LONG DenominatorOfTssiRatio);
+
+BOOLEAN GetDesiredTssiAndCurrentTssi(
+ IN struct _RTMP_ADAPTER *pAd,
+ INOUT PCHAR pDesiredTssi,
+ INOUT PCHAR pCurrentTssi);
+
+#endif /* RTMP_INTERNAL_TX_ALC */
+
+VOID RT5390_ChipAGCInit(
+ IN struct _RTMP_ADAPTER *pAd,
+ IN UCHAR BandWidth);
+
+VOID RT5392_AsicResetBBPAgent(
+ IN struct _RTMP_ADAPTER *pAd);
+
+VOID NICStoreBBPValue(
+ IN struct _RTMP_ADAPTER *pAd,
+ IN REG_PAIR *RegPair);
+
+VOID NICRestoreBBPValue(
+ IN struct _RTMP_ADAPTER *pAd,
+ IN REG_PAIR *RegPair);
+
+#endif /* defined(RT5370) || defined(RT5372) || defined(RT5390) || defined(RT5392) */
+#endif /* __RT5390_H__ */
diff --git a/cleopatre/devkit/rt5572drv/MODULE/include/chip/rt5592.h b/cleopatre/devkit/rt5572drv/MODULE/include/chip/rt5592.h
new file mode 100644
index 0000000000..45cfa68559
--- /dev/null
+++ b/cleopatre/devkit/rt5572drv/MODULE/include/chip/rt5592.h
@@ -0,0 +1,93 @@
+/****************************************************************************
+ * Ralink Tech Inc.
+ * 4F, No. 2 Technology 5th Rd.
+ * Science-based Industrial Park
+ * Hsin-chu, Taiwan, R.O.C.
+ * (c) Copyright 2002, Ralink Technology, Inc.
+ *
+ * All rights reserved. Ralink's source code is an unpublished work and the
+ * use of a copyright notice does not imply otherwise. This source code
+ * contains confidential trade secret material of Ralink Tech. Any attemp
+ * or participation in deciphering, decoding, reverse engineering or in any
+ * way altering the source code is stricitly prohibited, unless the prior
+ * written consent of Ralink Technology, Inc. is obtained.
+ ****************************************************************************
+
+ Module Name:
+ rt5592.h
+
+ Abstract:
+
+ Revision History:
+ Who When What
+ --------- ---------- ----------------------------------------------
+ */
+
+#ifndef __RT5592_H__
+#define __RT5592_H__
+
+#include "chip/rt30xx.h"
+
+#ifndef RTMP_RF_RW_SUPPORT
+#error "For RT5592, you should define the compile flag -DRTMP_RF_RW_SUPPORT"
+#endif
+
+#ifndef RT30xx
+#error "For RT5592, you should define the compile flag -DRT30xx"
+#endif
+
+#define BBP_REG_BF BBP_R163 // TxBf control
+#define BBP_REG_BF BBP_R163 // TxBf control
+
+
+#ifdef RTMP_FLASH_SUPPORT
+
+#ifdef RTMP_MAC_USB
+#define EEPROM_DEFAULT_FILE_PATH "/etc_ro/Wireless/RT2870AP/RT5572_USB_2T2R_V1_3.BIN"
+#endif /* RTMP_MAC_USB */
+
+#if defined (CONFIG_RT5592_AP_RF_OFFSET)
+#define RF_OFFSET CONFIG_RT5592_AP_RF_OFFSET
+#else
+#define RF_OFFSET 0x48000
+#endif
+#endif /* RTMP_FLASH_SUPPORT */
+
+#ifdef RT5592EP_SUPPORT
+#define RT5592_TYPE_EP 1
+#endif /* RT5592EP_SUPPORT */
+
+/*
+ * If MAC 0x5E8 bit[31] = 0, Xtal is 20M
+ * If MAC 0x5E8 bit[31] = 1, Xtal is 40M
+ */
+enum XTAL{
+ XTAL20M,
+ XTAL40M
+};
+
+/*
+ * Frequency plan item for RT5592
+ * N: R9[4], R8[7:0]
+ * K: R9[3:0]
+ * mod: R9[7], R11[3:2] (eg. mod=8 => 0x0, mod=10 => 0x2)
+ * R: R11[1:0] (eg. R=1 => 0x0, R=3 => 0x2)
+ */
+typedef struct _RT5592_FREQUENCY_ITEM {
+ UCHAR Channel;
+ UINT16 N;
+ UCHAR K;
+ UCHAR mod;
+ UCHAR R;
+} RT5592_FREQUENCY_ITEM, *PRT5592_FREQUENCY_ITEM;
+
+/* Frequency plan table */
+typedef struct _RT5592_FREQUENCY_PLAN {
+ const struct _RT5592_FREQUENCY_ITEM *pFrequencyPlan;
+ UCHAR totalFreqItem;
+} RT5592_FREQUENCY_PLAN, *PRT5592_FREQUENCY_PLAN;
+
+VOID RT5592_Init(
+ IN struct _RTMP_ADAPTER *pAd);
+
+#endif /* __RT5592_H__ */
diff --git a/cleopatre/devkit/rt5572drv/MODULE/include/chip/rtmp_mac.h b/cleopatre/devkit/rt5572drv/MODULE/include/chip/rtmp_mac.h
new file mode 100644
index 0000000000..00d6ee1188
--- /dev/null
+++ b/cleopatre/devkit/rt5572drv/MODULE/include/chip/rtmp_mac.h
@@ -0,0 +1,3181 @@
+/*
+ ***************************************************************************
+ * Ralink Tech Inc.
+ * 4F, No. 2 Technology 5th Rd.
+ * Science-based Industrial Park
+ * Hsin-chu, Taiwan, R.O.C.
+ *
+ * (c) Copyright 2002-2004, Ralink Technology, Inc.
+ *
+ * All rights reserved. Ralink's source code is an unpublished work and the
+ * use of a copyright notice does not imply otherwise. This source code
+ * contains confidential trade secret material of Ralink Tech. Any attemp
+ * or participation in deciphering, decoding, reverse engineering or in any
+ * way altering the source code is stricitly prohibited, unless the prior
+ * written consent of Ralink Technology, Inc. is obtained.
+ ***************************************************************************
+
+ Module Name:
+ rtmp_mac.h
+
+ Abstract:
+ Ralink Wireless Chip MAC related definition & structures
+
+ Revision History:
+ Who When What
+ -------- ---------- ----------------------------------------------
+*/
+
+#ifndef __RTMP_MAC_H__
+#define __RTMP_MAC_H__
+
+
+
+/* ================================================================================= */
+/* TX / RX ring descriptor format */
+/* ================================================================================= */
+
+/* the first 24-byte in TXD is called TXINFO and will be DMAed to MAC block through TXFIFO. */
+/* MAC block use this TXINFO to control the transmission behavior of this frame. */
+#define FIFO_MGMT 0
+#define FIFO_HCCA 1
+#define FIFO_EDCA 2
+
+
+/* */
+/* TXD Wireless Information format for Tx ring and Mgmt Ring */
+/* */
+/*txop : for txop mode */
+/* 0:txop for the MPDU frame will be handles by ASIC by register */
+/* 1/2/3:the MPDU frame is send after PIFS/backoff/SIFS */
+#ifdef RT_BIG_ENDIAN
+typedef struct GNU_PACKED _TXWI_STRUC {
+ /* Word 0 */
+ UINT32 PHYMODE:2;
+ UINT32 iTxBF:1; /* iTxBF enable */
+ UINT32 Sounding:1; /* Sounding enable */
+ UINT32 eTxBF:1; /* eTxBF enable */
+ UINT32 STBC:2; /*channel bandwidth 20MHz or 40 MHz */
+ UINT32 ShortGI:1;
+ UINT32 BW:1; /*channel bandwidth 20MHz or 40 MHz */
+ UINT32 MCS:7;
+
+ UINT32 rsv:1;
+ UINT32 TXRPT:1;
+ UINT32 Autofallback:1; /* TX rate auto fallback disable */
+ UINT32 NDPSndBW:1; /* NDP sounding BW */
+ UINT32 NDPSndRate:2; /* 0 : MCS0, 1: MCS8, 2: MCS16, 3: reserved */
+ UINT32 txop:2; /*tx back off mode 0:HT TXOP rule , 1:PIFS TX ,2:Backoff, 3:sifs only when previous frame exchange is successful. */
+ UINT32 MpduDensity:3;
+ UINT32 AMPDU:1;
+
+ UINT32 TS:1;
+ UINT32 CFACK:1;
+ UINT32 MIMOps:1; /* the remote peer is in dynamic MIMO-PS mode */
+ UINT32 FRAG:1; /* 1 to inform TKIP engine this is a fragment. */
+ /* Word 1 */
+ UINT32 PacketId:4;
+ UINT32 MPDUtotalByteCount:12;
+ UINT32 WirelessCliID:8;
+ UINT32 BAWinSize:6;
+ UINT32 NSEQ:1;
+ UINT32 ACK:1;
+ /* Word 2 */
+ UINT32 IV;
+ /* Word 3 */
+ UINT32 EIV;
+
+#ifdef RT5592
+ /* Word 4 */
+ /* For Expert Antenna */
+ UINT32 Reserved:11;
+ UINT32 CCP:1;
+ UINT32 TxPwrAdj:4;
+ UINT32 TxStreamMode:8;
+ UINT32 EncodedAntID:8;
+#endif /* RT5592 */
+} TXWI_STRUC, *PTXWI_STRUC;
+#else
+typedef struct GNU_PACKED _TXWI_STRUC {
+ /* Word 0 */
+ /* ex: 00 03 00 40 means txop = 3, PHYMODE = 1 */
+ UINT32 FRAG:1; /* 1 to inform TKIP engine this is a fragment. */
+ UINT32 MIMOps:1; /* the remote peer is in dynamic MIMO-PS mode */
+ UINT32 CFACK:1;
+ UINT32 TS:1;
+
+ UINT32 AMPDU:1;
+ UINT32 MpduDensity:3;
+ UINT32 txop:2; /*FOR "THIS" frame. 0:HT TXOP rule , 1:PIFS TX ,2:Backoff, 3:sifs only when previous frame exchange is successful. */
+ UINT32 NDPSndRate:2; /* 0 : MCS0, 1: MCS8, 2: MCS16, 3: reserved */
+ UINT32 NDPSndBW:1; /* NDP sounding BW */
+ UINT32 Autofallback:1; /* TX rate auto fallback disable */
+ UINT32 TXRPT:1;
+ UINT32 rsv:1;
+
+ UINT32 MCS:7;
+ UINT32 BW:1; /*channel bandwidth 20MHz or 40 MHz */
+ UINT32 ShortGI:1;
+ UINT32 STBC:2; /* 1: STBC support MCS =0-7, 2,3 : RESERVE */
+ UINT32 eTxBF:1; /* eTxBF enable */
+ UINT32 Sounding:1; /* Sounding enable */
+ UINT32 iTxBF:1; /* iTxBF enable */
+ UINT32 PHYMODE:2;
+ /* Word1 */
+ /* ex: 1c ff 38 00 means ACK=0, BAWinSize=7, MPDUtotalByteCount = 0x38 */
+ UINT32 ACK:1;
+ UINT32 NSEQ:1;
+ UINT32 BAWinSize:6;
+ UINT32 WirelessCliID:8;
+ UINT32 MPDUtotalByteCount:12;
+ UINT32 PacketId:4;
+ /*Word2 */
+ UINT32 IV;
+ /*Word3 */
+ UINT32 EIV;
+
+#ifdef RT5592
+ /* Word 4 */
+ /* For Expert Antenna */
+ UINT32 EncodedAntID:8;
+ UINT32 TxStreamMode:8;
+ UINT32 TxPwrAdj:4;
+ UINT32 CCP:1;
+ UINT32 Reserved:11;
+#endif /* RT5592 */
+} TXWI_STRUC, *PTXWI_STRUC;
+#endif
+
+
+/* */
+/* RXWI wireless information format, in PBF. invisible in driver. */
+/* */
+#ifdef RT_BIG_ENDIAN
+typedef struct GNU_PACKED _RXWI_STRUC {
+ /* Word 0 */
+ UINT32 TID:4;
+ UINT32 MPDUtotalByteCount:12;
+ UINT32 UDF:3;
+ UINT32 BSSID:3;
+ UINT32 KeyIndex:2;
+ UINT32 WirelessCliID:8;
+
+ /* Word 1 */
+ UINT32 PHYMODE:2; /* 1: this RX frame is unicast to me */
+ UINT32 iTxBF:1; /* iTxBF enable */
+ UINT32 Sounding:1; /* Sounding enable */
+ UINT32 eTxBF:1; /* eTxBF enable */
+ UINT32 STBC:2;
+ UINT32 ShortGI:1;
+ UINT32 BW:1;
+ UINT32 MCS:7;
+ UINT32 SEQUENCE:12;
+ UINT32 FRAG:4;
+
+ /* Word 2 */
+ UINT32 rsv1:8;
+ UINT32 RSSI2:8;
+ UINT32 RSSI1:8;
+ UINT32 RSSI0:8;
+
+ /* Word 3 */
+ UINT32 FOFFSET:8;
+ UINT32 SNR2:8;
+ UINT32 SNR1:8;
+ UINT32 SNR0:8;
+
+ UINT32 rsv3;
+
+#if defined(RT5592)
+ /* Word 5 */
+ /* For Exper Antenna */
+ UINT32 rsv4:24;
+ UINT32 EANT_ID:8;
+#endif /* RT5592 */
+} RXWI_STRUC, *PRXWI_STRUC;
+#else
+typedef struct GNU_PACKED _RXWI_STRUC {
+ /* Word 0 */
+ UINT32 WirelessCliID:8;
+ UINT32 KeyIndex:2;
+ UINT32 BSSID:3;
+ UINT32 UDF:3;
+ UINT32 MPDUtotalByteCount:12;
+ UINT32 TID:4;
+
+ /* Word 1 */
+ UINT32 FRAG:4;
+ UINT32 SEQUENCE:12;
+ UINT32 MCS:7;
+ UINT32 BW:1;
+ UINT32 ShortGI:1;
+ UINT32 STBC:2;
+ UINT32 eTxBF:1; /* eTxBF enable */
+ UINT32 Sounding:1; /* Sounding enable */
+ UINT32 iTxBF:1; /* iTxBF enable */
+ UINT32 PHYMODE:2; /* 1: this RX frame is unicast to me */
+
+ /*Word2 */
+ UINT32 RSSI0:8;
+ UINT32 RSSI1:8;
+ UINT32 RSSI2:8;
+ UINT32 rsv1:8;
+
+ /*Word3 */
+ UINT32 SNR0:8;
+ UINT32 SNR1:8;
+ UINT32 SNR2:8;
+ UINT32 FOFFSET:8;
+
+ UINT32 rsv3;
+
+#if defined(RT5592)
+ /* Word 5 */
+ /* For Exper Antenna */
+ UINT32 EANT_ID:8;
+ UINT32 rsv4:24;
+#endif /* RT5592 */
+} RXWI_STRUC, *PRXWI_STRUC;
+#endif
+
+
+/* ================================================================================= */
+/* Register format */
+/* ================================================================================= */
+
+
+#define SYSCFG0 0x10
+
+/* */
+/* PCI registers - base address 0x0000 */
+/* */
+#define PCI_CFG 0x0000
+#define PCI_EECTRL 0x0004
+#define PCI_MCUCTRL 0x0008
+#define AUX_CTRL 0x10c
+
+#define OPT_14 0x114
+
+/* */
+/* SCH/DMA registers - base address 0x0200 */
+/* */
+/* INT_SOURCE_CSR: Interrupt source register. Write one to clear corresponding bit */
+/* */
+#define DMA_CSR0 0x200
+#define INT_SOURCE_CSR 0x200
+#ifdef RT_BIG_ENDIAN
+typedef union _INT_SOURCE_CSR_STRUC {
+ struct {
+#ifdef CARRIER_DETECTION_SUPPORT
+ UINT32 :11;
+ UINT32 RadarINT:1;
+ UINT32 rsv:2;
+#else /* original source code */
+ UINT32 :14;
+#endif /* CARRIER_DETECTION_SUPPORT */
+ UINT32 TxCoherent:1;
+ UINT32 RxCoherent:1;
+ UINT32 GPTimer:1;
+ UINT32 AutoWakeup:1;/*bit14 */
+ UINT32 TXFifoStatusInt:1;/*FIFO Statistics is full, sw should read 0x171c */
+ UINT32 PreTBTT:1;
+ UINT32 TBTTInt:1;
+ UINT32 RxTxCoherent:1;
+ UINT32 MCUCommandINT:1;
+ UINT32 MgmtDmaDone:1;
+ UINT32 HccaDmaDone:1;
+ UINT32 Ac3DmaDone:1;
+ UINT32 Ac2DmaDone:1;
+ UINT32 Ac1DmaDone:1;
+ UINT32 Ac0DmaDone:1;
+ UINT32 RxDone:1;
+ UINT32 TxDelayINT:1; /*delayed interrupt, not interrupt until several int or time limit hit */
+ UINT32 RxDelayINT:1; /*dealyed interrupt */
+ } field;
+ UINT32 word;
+} INT_SOURCE_CSR_STRUC, *PINT_SOURCE_CSR_STRUC;
+#else
+typedef union _INT_SOURCE_CSR_STRUC {
+ struct {
+ UINT32 RxDelayINT:1;
+ UINT32 TxDelayINT:1;
+ UINT32 RxDone:1;
+ UINT32 Ac0DmaDone:1;/*4 */
+ UINT32 Ac1DmaDone:1;
+ UINT32 Ac2DmaDone:1;
+ UINT32 Ac3DmaDone:1;
+ UINT32 HccaDmaDone:1; /* bit7 */
+ UINT32 MgmtDmaDone:1;
+ UINT32 MCUCommandINT:1;/*bit 9 */
+ UINT32 RxTxCoherent:1;
+ UINT32 TBTTInt:1;
+ UINT32 PreTBTT:1;
+ UINT32 TXFifoStatusInt:1;/*FIFO Statistics is full, sw should read 0x171c */
+ UINT32 AutoWakeup:1;/*bit14 */
+ UINT32 GPTimer:1;
+ UINT32 RxCoherent:1;/*bit16 */
+ UINT32 TxCoherent:1;
+#ifdef CARRIER_DETECTION_SUPPORT
+ UINT32 rsv:2;
+ UINT32 RadarINT:1;
+ UINT32 :11;
+#else
+ UINT32 :14;
+#endif /* CARRIER_DETECTION_SUPPORT */
+ } field;
+ UINT32 word;
+} INT_SOURCE_CSR_STRUC, *PINT_SOURCE_CSR_STRUC;
+#endif
+
+/* */
+/* INT_MASK_CSR: Interrupt MASK register. 1: the interrupt is mask OFF */
+/* */
+#define INT_MASK_CSR 0x204
+#ifdef RT_BIG_ENDIAN
+typedef union _INT_MASK_CSR_STRUC {
+ struct {
+ UINT32 TxCoherent:1;
+ UINT32 RxCoherent:1;
+#ifdef CARRIER_DETECTION_SUPPORT
+ UINT32 :9;
+ UINT32 RadarINT:1;
+ UINT32 rsv:10;
+#else
+ UINT32 :20;
+#endif /* CARRIER_DETECTION_SUPPORT */
+ UINT32 MCUCommandINT:1;
+ UINT32 MgmtDmaDone:1;
+ UINT32 HccaDmaDone:1;
+ UINT32 Ac3DmaDone:1;
+ UINT32 Ac2DmaDone:1;
+ UINT32 Ac1DmaDone:1;
+ UINT32 Ac0DmaDone:1;
+ UINT32 RxDone:1;
+ UINT32 TxDelay:1;
+ UINT32 RXDelay_INT_MSK:1;
+ } field;
+ UINT32 word;
+}INT_MASK_CSR_STRUC, *PINT_MASK_CSR_STRUC;
+#else
+typedef union _INT_MASK_CSR_STRUC {
+ struct {
+ UINT32 RXDelay_INT_MSK:1;
+ UINT32 TxDelay:1;
+ UINT32 RxDone:1;
+ UINT32 Ac0DmaDone:1;
+ UINT32 Ac1DmaDone:1;
+ UINT32 Ac2DmaDone:1;
+ UINT32 Ac3DmaDone:1;
+ UINT32 HccaDmaDone:1;
+ UINT32 MgmtDmaDone:1;
+ UINT32 MCUCommandINT:1;
+#ifdef CARRIER_DETECTION_SUPPORT
+ UINT32 rsv:10;
+ UINT32 RadarINT:1;
+ UINT32 :9;
+#else
+ UINT32 :20;
+#endif /* CARRIER_DETECTION_SUPPORT */
+ UINT32 RxCoherent:1;
+ UINT32 TxCoherent:1;
+ } field;
+ UINT32 word;
+} INT_MASK_CSR_STRUC, *PINT_MASK_CSR_STRUC;
+#endif
+
+#define WPDMA_GLO_CFG 0x208
+#ifdef RT_BIG_ENDIAN
+typedef union _WPDMA_GLO_CFG_STRUC {
+ struct {
+ UINT32 HDR_SEG_LEN:16;
+ UINT32 RXHdrScater:8;
+ UINT32 BigEndian:1;
+ UINT32 EnTXWriteBackDDONE:1;
+ UINT32 WPDMABurstSIZE:2;
+ UINT32 RxDMABusy:1;
+ UINT32 EnableRxDMA:1;
+ UINT32 TxDMABusy:1;
+ UINT32 EnableTxDMA:1;
+ } field;
+ UINT32 word;
+}WPDMA_GLO_CFG_STRUC, *PWPDMA_GLO_CFG_STRUC;
+#else
+typedef union _WPDMA_GLO_CFG_STRUC {
+ struct {
+ UINT32 EnableTxDMA:1;
+ UINT32 TxDMABusy:1;
+ UINT32 EnableRxDMA:1;
+ UINT32 RxDMABusy:1;
+ UINT32 WPDMABurstSIZE:2;
+ UINT32 EnTXWriteBackDDONE:1;
+ UINT32 BigEndian:1;
+ UINT32 RXHdrScater:8;
+ UINT32 HDR_SEG_LEN:16;
+ } field;
+ UINT32 word;
+} WPDMA_GLO_CFG_STRUC, *PWPDMA_GLO_CFG_STRUC;
+#endif
+
+#define WPDMA_RST_IDX 0x20c
+#ifdef RT_BIG_ENDIAN
+typedef union _WPDMA_RST_IDX_STRUC {
+ struct {
+ UINT32 :15;
+ UINT32 RST_DRX_IDX0:1;
+ UINT32 rsv:10;
+ UINT32 RST_DTX_IDX5:1;
+ UINT32 RST_DTX_IDX4:1;
+ UINT32 RST_DTX_IDX3:1;
+ UINT32 RST_DTX_IDX2:1;
+ UINT32 RST_DTX_IDX1:1;
+ UINT32 RST_DTX_IDX0:1;
+ } field;
+ UINT32 word;
+}WPDMA_RST_IDX_STRUC, *PWPDMA_RST_IDX_STRUC;
+#else
+typedef union _WPDMA_RST_IDX_STRUC {
+ struct {
+ UINT32 RST_DTX_IDX0:1;
+ UINT32 RST_DTX_IDX1:1;
+ UINT32 RST_DTX_IDX2:1;
+ UINT32 RST_DTX_IDX3:1;
+ UINT32 RST_DTX_IDX4:1;
+ UINT32 RST_DTX_IDX5:1;
+ UINT32 rsv:10;
+ UINT32 RST_DRX_IDX0:1;
+ UINT32 :15;
+ } field;
+ UINT32 word;
+} WPDMA_RST_IDX_STRUC, *PWPDMA_RST_IDX_STRUC;
+#endif
+#define DELAY_INT_CFG 0x0210
+#ifdef RT_BIG_ENDIAN
+typedef union _DELAY_INT_CFG_STRUC {
+ struct {
+ UINT32 TXDLY_INT_EN:1;
+ UINT32 TXMAX_PINT:7;
+ UINT32 TXMAX_PTIME:8;
+ UINT32 RXDLY_INT_EN:1;
+ UINT32 RXMAX_PINT:7;
+ UINT32 RXMAX_PTIME:8;
+ } field;
+ UINT32 word;
+}DELAY_INT_CFG_STRUC, *PDELAY_INT_CFG_STRUC;
+#else
+typedef union _DELAY_INT_CFG_STRUC {
+ struct {
+ UINT32 RXMAX_PTIME:8;
+ UINT32 RXMAX_PINT:7;
+ UINT32 RXDLY_INT_EN:1;
+ UINT32 TXMAX_PTIME:8;
+ UINT32 TXMAX_PINT:7;
+ UINT32 TXDLY_INT_EN:1;
+ } field;
+ UINT32 word;
+} DELAY_INT_CFG_STRUC, *PDELAY_INT_CFG_STRUC;
+#endif
+#define WMM_AIFSN_CFG 0x0214
+#ifdef RT_BIG_ENDIAN
+typedef union _AIFSN_CSR_STRUC {
+ struct {
+ UINT32 Rsv:16;
+ UINT32 Aifsn3:4; /* for AC_VO */
+ UINT32 Aifsn2:4; /* for AC_VI */
+ UINT32 Aifsn1:4; /* for AC_BK */
+ UINT32 Aifsn0:4; /* for AC_BE */
+ } field;
+ UINT32 word;
+} AIFSN_CSR_STRUC, *PAIFSN_CSR_STRUC;
+#else
+typedef union _AIFSN_CSR_STRUC {
+ struct {
+ UINT32 Aifsn0:4; /* for AC_BE */
+ UINT32 Aifsn1:4; /* for AC_BK */
+ UINT32 Aifsn2:4; /* for AC_VI */
+ UINT32 Aifsn3:4; /* for AC_VO */
+ UINT32 Rsv:16;
+ } field;
+ UINT32 word;
+} AIFSN_CSR_STRUC, *PAIFSN_CSR_STRUC;
+#endif
+/* */
+/* CWMIN_CSR: CWmin for each EDCA AC */
+/* */
+#define WMM_CWMIN_CFG 0x0218
+#ifdef RT_BIG_ENDIAN
+typedef union _CWMIN_CSR_STRUC {
+ struct {
+ UINT32 Rsv:16;
+ UINT32 Cwmin3:4; /* for AC_VO */
+ UINT32 Cwmin2:4; /* for AC_VI */
+ UINT32 Cwmin1:4; /* for AC_BK */
+ UINT32 Cwmin0:4; /* for AC_BE */
+ } field;
+ UINT32 word;
+} CWMIN_CSR_STRUC, *PCWMIN_CSR_STRUC;
+#else
+typedef union _CWMIN_CSR_STRUC {
+ struct {
+ UINT32 Cwmin0:4; /* for AC_BE */
+ UINT32 Cwmin1:4; /* for AC_BK */
+ UINT32 Cwmin2:4; /* for AC_VI */
+ UINT32 Cwmin3:4; /* for AC_VO */
+ UINT32 Rsv:16;
+ } field;
+ UINT32 word;
+} CWMIN_CSR_STRUC, *PCWMIN_CSR_STRUC;
+#endif
+
+/* */
+/* CWMAX_CSR: CWmin for each EDCA AC */
+/* */
+#define WMM_CWMAX_CFG 0x021c
+#ifdef RT_BIG_ENDIAN
+typedef union _CWMAX_CSR_STRUC {
+ struct {
+ UINT32 Rsv:16;
+ UINT32 Cwmax3:4; /* for AC_VO */
+ UINT32 Cwmax2:4; /* for AC_VI */
+ UINT32 Cwmax1:4; /* for AC_BK */
+ UINT32 Cwmax0:4; /* for AC_BE */
+ } field;
+ UINT32 word;
+} CWMAX_CSR_STRUC, *PCWMAX_CSR_STRUC;
+#else
+typedef union _CWMAX_CSR_STRUC {
+ struct {
+ UINT32 Cwmax0:4; /* for AC_BE */
+ UINT32 Cwmax1:4; /* for AC_BK */
+ UINT32 Cwmax2:4; /* for AC_VI */
+ UINT32 Cwmax3:4; /* for AC_VO */
+ UINT32 Rsv:16;
+ } field;
+ UINT32 word;
+} CWMAX_CSR_STRUC, *PCWMAX_CSR_STRUC;
+#endif
+
+
+/* */
+/* AC_TXOP_CSR0: AC_BK/AC_BE TXOP register */
+/* */
+#define WMM_TXOP0_CFG 0x0220
+#ifdef RT_BIG_ENDIAN
+typedef union _AC_TXOP_CSR0_STRUC {
+ struct {
+ USHORT Ac1Txop; /* for AC_BE, in unit of 32us */
+ USHORT Ac0Txop; /* for AC_BK, in unit of 32us */
+ } field;
+ UINT32 word;
+} AC_TXOP_CSR0_STRUC, *PAC_TXOP_CSR0_STRUC;
+#else
+typedef union _AC_TXOP_CSR0_STRUC {
+ struct {
+ USHORT Ac0Txop; /* for AC_BK, in unit of 32us */
+ USHORT Ac1Txop; /* for AC_BE, in unit of 32us */
+ } field;
+ UINT32 word;
+} AC_TXOP_CSR0_STRUC, *PAC_TXOP_CSR0_STRUC;
+#endif
+
+/* */
+/* AC_TXOP_CSR1: AC_VO/AC_VI TXOP register */
+/* */
+#define WMM_TXOP1_CFG 0x0224
+#ifdef RT_BIG_ENDIAN
+typedef union _AC_TXOP_CSR1_STRUC {
+ struct {
+ USHORT Ac3Txop; /* for AC_VO, in unit of 32us */
+ USHORT Ac2Txop; /* for AC_VI, in unit of 32us */
+ } field;
+ UINT32 word;
+} AC_TXOP_CSR1_STRUC, *PAC_TXOP_CSR1_STRUC;
+#else
+typedef union _AC_TXOP_CSR1_STRUC {
+ struct {
+ USHORT Ac2Txop; /* for AC_VI, in unit of 32us */
+ USHORT Ac3Txop; /* for AC_VO, in unit of 32us */
+ } field;
+ UINT32 word;
+} AC_TXOP_CSR1_STRUC, *PAC_TXOP_CSR1_STRUC;
+#endif
+
+
+#define RINGREG_DIFF 0x10
+#define GPIO_CTRL_CFG 0x0228 /*MAC_CSR13 */
+#define MCU_CMD_CFG 0x022c
+#define TX_BASE_PTR0 0x0230 /*AC_BK base address */
+#define TX_MAX_CNT0 0x0234
+#define TX_CTX_IDX0 0x0238
+#define TX_DTX_IDX0 0x023c
+#define TX_BASE_PTR1 0x0240 /*AC_BE base address */
+#define TX_MAX_CNT1 0x0244
+#define TX_CTX_IDX1 0x0248
+#define TX_DTX_IDX1 0x024c
+#define TX_BASE_PTR2 0x0250 /*AC_VI base address */
+#define TX_MAX_CNT2 0x0254
+#define TX_CTX_IDX2 0x0258
+#define TX_DTX_IDX2 0x025c
+#define TX_BASE_PTR3 0x0260 /*AC_VO base address */
+#define TX_MAX_CNT3 0x0264
+#define TX_CTX_IDX3 0x0268
+#define TX_DTX_IDX3 0x026c
+#define TX_BASE_PTR4 0x0270 /*HCCA base address */
+#define TX_MAX_CNT4 0x0274
+#define TX_CTX_IDX4 0x0278
+#define TX_DTX_IDX4 0x027c
+#define TX_BASE_PTR5 0x0280 /*MGMT base address */
+#define TX_MAX_CNT5 0x0284
+#define TX_CTX_IDX5 0x0288
+#define TX_DTX_IDX5 0x028c
+#define TX_MGMTMAX_CNT TX_MAX_CNT5
+#define TX_MGMTCTX_IDX TX_CTX_IDX5
+#define TX_MGMTDTX_IDX TX_DTX_IDX5
+#define RX_BASE_PTR 0x0290 /*RX base address */
+#define RX_MAX_CNT 0x0294
+#define RX_CRX_IDX 0x0298
+#define RX_DRX_IDX 0x029c
+
+
+#define USB_DMA_CFG 0x02a0
+#ifdef RT_BIG_ENDIAN
+typedef union _USB_DMA_CFG_STRUC {
+ struct {
+ UINT32 TxBusy:1; /*USB DMA TX FSM busy . debug only */
+ UINT32 RxBusy:1; /*USB DMA RX FSM busy . debug only */
+ UINT32 EpoutValid:6; /*OUT endpoint data valid. debug only */
+ UINT32 TxBulkEn:1; /*Enable USB DMA Tx */
+ UINT32 RxBulkEn:1; /*Enable USB DMA Rx */
+ UINT32 RxBulkAggEn:1; /*Enable Rx Bulk Aggregation */
+ UINT32 TxopHalt:1; /*Halt TXOP count down when TX buffer is full. */
+ UINT32 TxClear:1; /*Clear USB DMA TX path */
+ UINT32 rsv:2;
+ UINT32 phyclear:1; /*phy watch dog enable. write 1 */
+ UINT32 RxBulkAggLmt:8; /*Rx Bulk Aggregation Limit in unit of 1024 bytes */
+ UINT32 RxBulkAggTOut:8; /*Rx Bulk Aggregation TimeOut in unit of 33ns */
+ } field;
+ UINT32 word;
+} USB_DMA_CFG_STRUC, *PUSB_DMA_CFG_STRUC;
+#else
+typedef union _USB_DMA_CFG_STRUC {
+ struct {
+ UINT32 RxBulkAggTOut:8; /*Rx Bulk Aggregation TimeOut in unit of 33ns */
+ UINT32 RxBulkAggLmt:8; /*Rx Bulk Aggregation Limit in unit of 256 bytes */
+ UINT32 phyclear:1; /*phy watch dog enable. write 1 */
+ UINT32 rsv:2;
+ UINT32 TxClear:1; /*Clear USB DMA TX path */
+ UINT32 TxopHalt:1; /*Halt TXOP count down when TX buffer is full. */
+ UINT32 RxBulkAggEn:1; /*Enable Rx Bulk Aggregation */
+ UINT32 RxBulkEn:1; /*Enable USB DMA Rx */
+ UINT32 TxBulkEn:1; /*Enable USB DMA Tx */
+ UINT32 EpoutValid:6; /*OUT endpoint data valid */
+ UINT32 RxBusy:1; /*USB DMA RX FSM busy */
+ UINT32 TxBusy:1; /*USB DMA TX FSM busy */
+ } field;
+ UINT32 word;
+} USB_DMA_CFG_STRUC, *PUSB_DMA_CFG_STRUC;
+#endif
+
+#define US_CYC_CNT 0x02a4
+#ifdef BIG_ENDIAN
+typedef union _US_CYC_CNT_STRUC {
+ struct {
+ ULONG rsv2:7;
+ ULONG TestEn:1;
+ ULONG TestSel:8;
+ ULONG rsv1:7;
+ ULONG MiscModeEn:1;
+ ULONG UsCycCnt:8;
+ } field;
+ ULONG word;
+} US_CYC_CNT_STRUC, *PUS_CYC_CNT_STRUC;
+#else
+typedef union _US_CYC_CNT_STRUC {
+ struct {
+ ULONG UsCycCnt:8;
+ ULONG MiscModeEn:1;
+ ULONG rsv1:7;
+ ULONG TestSel:8;
+ ULONG TestEn:1;
+ ULONG rsv2:7;
+ } field;
+ ULONG word;
+} US_CYC_CNT_STRUC, *PUS_CYC_CNT_STRUC;
+#endif
+
+/* */
+/* 3 PBF registers */
+/* */
+/* */
+/* Most are for debug. Driver doesn't touch PBF register. */
+#define PBF_SYS_CTRL 0x0400
+
+#ifdef RT_BIG_ENDIAN
+typedef union _PBF_SYS_CTRL_STRUC
+{
+ struct
+ {
+ ULONG Reserved5:12; /* Reserved */
+ ULONG SHR_MSEL:1; /* Shared memory access selection */
+ ULONG PBF_MSEL:2; /* Packet buffer memory access selection */
+ ULONG HST_PM_SEL:1; /* The write selection of the host program RAM */
+ ULONG Reserved4:1; /* Reserved */
+ ULONG CAP_MODE:1; /* Packet buffer capture mode */
+ ULONG Reserved3:1; /* Reserved */
+ ULONG CLK_SEL:1; /* MAC/PBF clock source selection */
+ ULONG PBF_CLK_EN:1; /* PBF clock enable */
+ ULONG MAC_CLK_EN:1; /* MAC clock enable */
+ ULONG DMA_CLK_EN:1; /* DMA clock enable */
+ ULONG Reserved2:1; /* Reserved */
+ ULONG MCU_READY:1; /* MCU ready */
+ ULONG Reserved1:2; /* Reserved */
+ ULONG ASY_RESET:1; /* ASYNC interface reset */
+ ULONG PBF_RESET:1; /* PBF hardware reset */
+ ULONG MAC_RESET:1; /* MAC hardware reset */
+ ULONG DMA_RESET:1; /* DMA hardware reset */
+ ULONG MCU_RESET:1; /* MCU hardware reset */
+ } field;
+
+ ULONG word;
+} PBF_SYS_CTRL_STRUC, *PPBF_SYS_CTRL_STRUC;
+#else
+typedef union _PBF_SYS_CTRL_STRUC
+{
+ struct
+ {
+ ULONG MCU_RESET:1; /* MCU hardware reset */
+ ULONG DMA_RESET:1; /* DMA hardware reset */
+ ULONG MAC_RESET:1; /* MAC hardware reset */
+ ULONG PBF_RESET:1; /* PBF hardware reset */
+ ULONG ASY_RESET:1; /* ASYNC interface reset */
+ ULONG Reserved1:2; /* Reserved */
+ ULONG MCU_READY:1; /* MCU ready */
+ ULONG Reserved2:1; /* Reserved */
+ ULONG DMA_CLK_EN:1; /* DMA clock enable */
+ ULONG MAC_CLK_EN:1; /* MAC clock enable */
+ ULONG PBF_CLK_EN:1; /* PBF clock enable */
+ ULONG CLK_SEL:1; /* MAC/PBF clock source selection */
+ ULONG Reserved3:1; /* Reserved */
+ ULONG CAP_MODE:1; /* Packet buffer capture mode */
+ ULONG Reserved4:1; /* Reserved */
+ ULONG HST_PM_SEL:1; /* The write selection of the host program RAM */
+ ULONG PBF_MSEL:2; /* Packet buffer memory access selection */
+ ULONG SHR_MSEL:1; /* Shared memory access selection */
+ ULONG Reserved5:12; /* Reserved */
+ } field;
+
+ ULONG word;
+} PBF_SYS_CTRL_STRUC, *PPBF_SYS_CTRL_STRUC;
+#endif
+
+#define PBF_CFG 0x0408
+#define PBF_MAX_PCNT 0x040C
+#define PBF_CTRL 0x0410
+#define PBF_INT_STA 0x0414
+#define PBF_INT_ENA 0x0418
+#define TXRXQ_PCNT 0x0438
+#define PBF_DBG 0x043c
+#define PBF_CAP_CTRL 0x0440
+
+#ifdef RT30xx
+#ifdef RTMP_EFUSE_SUPPORT
+/* eFuse registers */
+#define EFUSE_CTRL 0x0580
+#define EFUSE_DATA0 0x0590
+#define EFUSE_DATA1 0x0594
+#define EFUSE_DATA2 0x0598
+#define EFUSE_DATA3 0x059c
+#endif /* RTMP_EFUSE_SUPPORT */
+#endif /* RT30xx */
+
+#define OSC_CTRL 0x5a4
+#define PCIE_PHY_TX_ATTENUATION_CTRL 0x05C8
+#define INTERNAL_1 0x05C8
+
+#ifdef RT_BIG_ENDIAN
+typedef union _INTERNAL_1_STRUCT
+{
+ struct
+ {
+ UINT32 Reserve1:10;
+ UINT32 CSO_RX_IPV6_CHKSUM_EN:1;
+ UINT32 CSO_TX_IPV6_CHKSUM_EN:1;
+ UINT32 CSO_HW_PARSE_TCP:1;
+ UINT32 CSO_HW_PARSE_IP:1;
+ UINT32 CSO_RX_CHKSUM_EN:1;
+ UINT32 CSO_TX_CHKSUM_EN:1;
+ UINT32 CSO_TIMEOUT_VALUE:4;
+ UINT32 PCIE_PHY_TX_ATTEN_EN:1;
+ UINT32 PCIE_PHY_TX_ATTEN_VALUE:3;
+ UINT32 Reserve2:7;
+ UINT32 RF_ISOLATION_ENABLE:1;
+ } field;
+
+ UINT32 word;
+} INTERNAL_1_STRUCT, *PINTERNAL_1_STRUCT;
+#else
+typedef union _TX_ATTENUATION_CTRL_STRUC {
+ struct
+ {
+ UINT32 RF_ISOLATION_ENABLE:1;
+ UINT32 Reserve2:7;
+ UINT32 PCIE_PHY_TX_ATTEN_VALUE:3;
+ UINT32 PCIE_PHY_TX_ATTEN_EN:1;
+ UINT32 CSO_TIMEOUT_VALUE:4;
+ UINT32 CSO_TX_CHKSUM_EN:1;
+ UINT32 CSO_RX_CHKSUM_EN:1;
+ UINT32 CSO_HW_PARSE_IP:1;
+ UINT32 CSO_HW_PARSE_TCP:1;
+ UINT32 CSO_TX_IPV6_CHKSUM_EN:1;
+ UINT32 CSO_RX_IPV6_CHKSUM_EN:1;
+ UINT32 Reserve1:10;
+ } field;
+
+ UINT32 word;
+} INTERNAL_1_STRUCT, *PINTERNAL_1_STRUCT;
+#endif
+
+#define LDO_CFG0 0x05d4
+#define GPIO_SWITCH 0x05dc
+
+#define DEBUG_INDEX 0x05e8
+
+/* */
+/* 4 MAC registers */
+/* */
+/* */
+/* 4.1 MAC SYSTEM configuration registers (offset:0x1000) */
+/* */
+#define MAC_CSR0 0x1000
+#ifdef RT_BIG_ENDIAN
+typedef union _ASIC_VER_ID_STRUC {
+ struct {
+ USHORT ASICVer; /* version : 2860 */
+ USHORT ASICRev; /* reversion : 0 */
+ } field;
+ UINT32 word;
+} ASIC_VER_ID_STRUC, *PASIC_VER_ID_STRUC;
+#else
+typedef union _ASIC_VER_ID_STRUC {
+ struct {
+ USHORT ASICRev; /* reversion : 0 */
+ USHORT ASICVer; /* version : 2860 */
+ } field;
+ UINT32 word;
+} ASIC_VER_ID_STRUC, *PASIC_VER_ID_STRUC;
+#endif
+#define MAC_SYS_CTRL 0x1004 /*MAC_CSR1 */
+#define MAC_ADDR_DW0 0x1008 /* MAC ADDR DW0 */
+#define MAC_ADDR_DW1 0x100c /* MAC ADDR DW1 */
+/* */
+/* MAC_CSR2: STA MAC register 0 */
+/* */
+#ifdef RT_BIG_ENDIAN
+typedef union _MAC_DW0_STRUC {
+ struct {
+ UCHAR Byte3; /* MAC address byte 3 */
+ UCHAR Byte2; /* MAC address byte 2 */
+ UCHAR Byte1; /* MAC address byte 1 */
+ UCHAR Byte0; /* MAC address byte 0 */
+ } field;
+ UINT32 word;
+} MAC_DW0_STRUC, *PMAC_DW0_STRUC;
+#else
+typedef union _MAC_DW0_STRUC {
+ struct {
+ UCHAR Byte0; /* MAC address byte 0 */
+ UCHAR Byte1; /* MAC address byte 1 */
+ UCHAR Byte2; /* MAC address byte 2 */
+ UCHAR Byte3; /* MAC address byte 3 */
+ } field;
+ UINT32 word;
+} MAC_DW0_STRUC, *PMAC_DW0_STRUC;
+#endif
+
+/* */
+/* MAC_CSR3: STA MAC register 1 */
+/* */
+#ifdef RT_BIG_ENDIAN
+typedef union _MAC_DW1_STRUC {
+ struct {
+ UCHAR Rsvd1;
+ UCHAR U2MeMask;
+ UCHAR Byte5; /* MAC address byte 5 */
+ UCHAR Byte4; /* MAC address byte 4 */
+ } field;
+ UINT32 word;
+} MAC_DW1_STRUC, *PMAC_DW1_STRUC;
+#else
+typedef union _MAC_DW1_STRUC {
+ struct {
+ UCHAR Byte4; /* MAC address byte 4 */
+ UCHAR Byte5; /* MAC address byte 5 */
+ UCHAR U2MeMask;
+ UCHAR Rsvd1;
+ } field;
+ UINT32 word;
+} MAC_DW1_STRUC, *PMAC_DW1_STRUC;
+#endif
+
+#define MAC_BSSID_DW0 0x1010 /* MAC BSSID DW0 */
+#define MAC_BSSID_DW1 0x1014 /* MAC BSSID DW1 */
+
+/* */
+/* MAC_CSR5: BSSID register 1 */
+/* */
+#ifdef RT_BIG_ENDIAN
+typedef union _MAC_CSR5_STRUC {
+ struct {
+ USHORT Rsvd:11;
+ USHORT MBssBcnNum:3;
+ USHORT BssIdMode:2; /* 0: one BSSID, 10: 4 BSSID, 01: 2 BSSID , 11: 8BSSID */
+ UCHAR Byte5; /* BSSID byte 5 */
+ UCHAR Byte4; /* BSSID byte 4 */
+ } field;
+ UINT32 word;
+} MAC_CSR5_STRUC, *PMAC_CSR5_STRUC;
+#else
+typedef union _MAC_CSR5_STRUC {
+ struct {
+ UCHAR Byte4; /* BSSID byte 4 */
+ UCHAR Byte5; /* BSSID byte 5 */
+ USHORT BssIdMask:2; /* 0: one BSSID, 10: 4 BSSID, 01: 2 BSSID , 11: 8BSSID */
+ USHORT MBssBcnNum:3;
+ USHORT Rsvd:11;
+ } field;
+ UINT32 word;
+} MAC_CSR5_STRUC, *PMAC_CSR5_STRUC;
+#endif
+
+#define MAX_LEN_CFG 0x1018 /* rt2860b max 16k bytes. bit12:13 Maximum PSDU length (power factor) 0:2^13, 1:2^14, 2:2^15, 3:2^16 */
+#define BBP_CSR_CFG 0x101c /* */
+/* */
+/* BBP_CSR_CFG: BBP serial control register */
+/* */
+#ifdef RT_BIG_ENDIAN
+typedef union _BBP_CSR_CFG_STRUC {
+ struct {
+ UINT32 :12;
+ UINT32 BBP_RW_MODE:1; /* 0: use serial mode 1:parallel */
+ UINT32 BBP_PAR_DUR:1; /* 0: 4 MAC clock cycles 1: 8 MAC clock cycles */
+ UINT32 Busy:1; /* 1: ASIC is busy execute BBP programming. */
+ UINT32 fRead:1; /* 0: Write BBP, 1: Read BBP */
+ UINT32 RegNum:8; /* Selected BBP register */
+ UINT32 Value:8; /* Register value to program into BBP */
+ } field;
+ UINT32 word;
+} BBP_CSR_CFG_STRUC, *PBBP_CSR_CFG_STRUC;
+#else
+typedef union _BBP_CSR_CFG_STRUC {
+ struct {
+ UINT32 Value:8; /* Register value to program into BBP */
+ UINT32 RegNum:8; /* Selected BBP register */
+ UINT32 fRead:1; /* 0: Write BBP, 1: Read BBP */
+ UINT32 Busy:1; /* 1: ASIC is busy execute BBP programming. */
+ UINT32 BBP_PAR_DUR:1; /* 0: 4 MAC clock cycles 1: 8 MAC clock cycles */
+ UINT32 BBP_RW_MODE:1; /* 0: use serial mode 1:parallel */
+ UINT32 :12;
+ } field;
+ UINT32 word;
+} BBP_CSR_CFG_STRUC, *PBBP_CSR_CFG_STRUC;
+#endif
+#define RF_CSR_CFG0 0x1020
+/* */
+/* RF_CSR_CFG: RF control register */
+/* */
+#ifdef RT_BIG_ENDIAN
+typedef union _RF_CSR_CFG0_STRUC {
+ struct {
+ UINT32 Busy:1; /* 0: idle 1: 8busy */
+ UINT32 Sel:1; /* 0:RF_LE0 activate 1:RF_LE1 activate */
+ UINT32 StandbyMode:1; /* 0: high when stand by 1: low when standby */
+ UINT32 bitwidth:5; /* Selected BBP register */
+ UINT32 RegIdAndContent:24; /* Register value to program into BBP */
+ } field;
+ UINT32 word;
+} RF_CSR_CFG0_STRUC, *PRF_CSR_CFG0_STRUC;
+#else
+typedef union _RF_CSR_CFG0_STRUC {
+ struct {
+ UINT32 RegIdAndContent:24; /* Register value to program into BBP */
+ UINT32 bitwidth:5; /* Selected BBP register */
+ UINT32 StandbyMode:1; /* 0: high when stand by 1: low when standby */
+ UINT32 Sel:1; /* 0:RF_LE0 activate 1:RF_LE1 activate */
+ UINT32 Busy:1; /* 0: idle 1: 8busy */
+ } field;
+ UINT32 word;
+} RF_CSR_CFG0_STRUC, *PRF_CSR_CFG0_STRUC;
+#endif
+#define RF_CSR_CFG1 0x1024
+#ifdef RT_BIG_ENDIAN
+typedef union _RF_CSR_CFG1_STRUC {
+ struct {
+ UINT32 rsv:7; /* 0: idle 1: 8busy */
+ UINT32 RFGap:5; /* Gap between BB_CONTROL_RF and RF_LE. 0: 3 system clock cycle (37.5usec) 1: 5 system clock cycle (62.5usec) */
+ UINT32 RegIdAndContent:24; /* Register value to program into BBP */
+ } field;
+ UINT32 word;
+} RF_CSR_CFG1_STRUC, *PRF_CSR_CFG1_STRUC;
+#else
+typedef union _RF_CSR_CFG1_STRUC {
+ struct {
+ UINT32 RegIdAndContent:24; /* Register value to program into BBP */
+ UINT32 RFGap:5; /* Gap between BB_CONTROL_RF and RF_LE. 0: 3 system clock cycle (37.5usec) 1: 5 system clock cycle (62.5usec) */
+ UINT32 rsv:7; /* 0: idle 1: 8busy */
+ } field;
+ UINT32 word;
+} RF_CSR_CFG1_STRUC, *PRF_CSR_CFG1_STRUC;
+#endif
+#define RF_CSR_CFG2 0x1028 /* */
+#ifdef RT_BIG_ENDIAN
+typedef union _RF_CSR_CFG2_STRUC {
+ struct {
+ UINT32 rsv:8; /* 0: idle 1: 8busy */
+ UINT32 RegIdAndContent:24; /* Register value to program into BBP */
+ } field;
+ UINT32 word;
+} RF_CSR_CFG2_STRUC, *PRF_CSR_CFG2_STRUC;
+#else
+typedef union _RF_CSR_CFG2_STRUC {
+ struct {
+ UINT32 RegIdAndContent:24; /* Register value to program into BBP */
+ UINT32 rsv:8; /* 0: idle 1: 8busy */
+ } field;
+ UINT32 word;
+} RF_CSR_CFG2_STRUC, *PRF_CSR_CFG2_STRUC;
+#endif
+#define LED_CFG 0x102c /* MAC_CSR14 */
+#ifdef RT_BIG_ENDIAN
+typedef union _LED_CFG_STRUC {
+ struct {
+ UINT32 :1;
+ UINT32 LedPolar:1; /* Led Polarity. 0: active low1: active high */
+ UINT32 YLedMode:2; /* yellow Led Mode */
+ UINT32 GLedMode:2; /* green Led Mode */
+ UINT32 RLedMode:2; /* red Led Mode 0: off1: blinking upon TX2: periodic slow blinking3: always on */
+ UINT32 rsv:2;
+ UINT32 SlowBlinkPeriod:6; /* slow blinking period. unit:1ms */
+ UINT32 OffPeriod:8; /* blinking off period unit 1ms */
+ UINT32 OnPeriod:8; /* blinking on period unit 1ms */
+ } field;
+ UINT32 word;
+} LED_CFG_STRUC, *PLED_CFG_STRUC;
+#else
+typedef union _LED_CFG_STRUC {
+ struct {
+ UINT32 OnPeriod:8; /* blinking on period unit 1ms */
+ UINT32 OffPeriod:8; /* blinking off period unit 1ms */
+ UINT32 SlowBlinkPeriod:6; /* slow blinking period. unit:1ms */
+ UINT32 rsv:2;
+ UINT32 RLedMode:2; /* red Led Mode 0: off1: blinking upon TX2: periodic slow blinking3: always on */
+ UINT32 GLedMode:2; /* green Led Mode */
+ UINT32 YLedMode:2; /* yellow Led Mode */
+ UINT32 LedPolar:1; /* Led Polarity. 0: active low1: active high */
+ UINT32 :1;
+ } field;
+ UINT32 word;
+} LED_CFG_STRUC, *PLED_CFG_STRUC;
+#endif
+
+/* */
+/* The number of the Tx chains */
+/* */
+#define NUM_OF_TX_CHAIN 4
+
+#define TX_CHAIN_ADDR0_L 0x1044 /* Stream mode MAC address registers */
+#define TX_CHAIN_ADDR0_H 0x1048
+#define TX_CHAIN_ADDR1_L 0x104C
+#define TX_CHAIN_ADDR1_H 0x1050
+#define TX_CHAIN_ADDR2_L 0x1054
+#define TX_CHAIN_ADDR2_H 0x1058
+#define TX_CHAIN_ADDR3_L 0x105C
+#define TX_CHAIN_ADDR3_H 0x1060
+
+#ifdef RT_BIG_ENDIAN
+typedef union _TX_CHAIN_ADDR0_L_STRUC
+{
+ struct
+ {
+ UCHAR TxChainAddr0L_Byte3; /* Destination MAC address of Tx chain0 (byte 3) */
+ UCHAR TxChainAddr0L_Byte2; /* Destination MAC address of Tx chain0 (byte 2) */
+ UCHAR TxChainAddr0L_Byte1; /* Destination MAC address of Tx chain0 (byte 1) */
+ UCHAR TxChainAddr0L_Byte0; /* Destination MAC address of Tx chain0 (byte 0) */
+ } field;
+
+ UINT32 word;
+} TX_CHAIN_ADDR0_L_STRUC, *PTX_CHAIN_ADDR0_L_STRUC;
+#else
+typedef union _TX_CHAIN_ADDR0_L_STRUC
+{
+ struct
+ {
+ UCHAR TxChainAddr0L_Byte0; /* Destination MAC address of Tx chain0 (byte 0) */
+ UCHAR TxChainAddr0L_Byte1; /* Destination MAC address of Tx chain0 (byte 1) */
+ UCHAR TxChainAddr0L_Byte2; /* Destination MAC address of Tx chain0 (byte 2) */
+ UCHAR TxChainAddr0L_Byte3; /* Destination MAC address of Tx chain0 (byte 3) */
+ } field;
+
+ UINT32 word;
+} TX_CHAIN_ADDR0_L_STRUC, *PTX_CHAIN_ADDR0_L_STRUC;
+#endif
+
+#define TX_CHAIN_ADDR0_H 0x1048
+
+#ifdef RT_BIG_ENDIAN
+typedef union _TX_CHAIN_ADDR0_H_STRUC
+{
+ struct
+ {
+ USHORT Reserved:12; /* Reserved */
+ USHORT TxChainSel0:4; /* Selection value of Tx chain0 */
+ UCHAR TxChainAddr0H_Byte5; /* Destination MAC address of Tx chain0 (byte 5) */
+ UCHAR TxChainAddr0H_Byte4; /* Destination MAC address of Tx chain0 (byte 4) */
+ } field;
+
+ UINT32 word;
+} TX_CHAIN_ADDR0_H_STRUC, *PTX_CHAIN_ADDR0_H_STRUC;
+#else
+typedef union _TX_CHAIN_ADDR0_H_STRUC
+{
+ struct
+ {
+ UCHAR TxChainAddr0H_Byte4; /* Destination MAC address of Tx chain0 (byte 4) */
+ UCHAR TxChainAddr0H_Byte5; /* Destination MAC address of Tx chain0 (byte 5) */
+ USHORT TxChainSel0:4; /* Selection value of Tx chain0 */
+ USHORT Reserved:12; /* Reserved */
+ } field;
+
+ UINT32 word;
+} TX_CHAIN_ADDR0_H_STRUC, *PTX_CHAIN_ADDR0_HA_STRUC;
+#endif
+
+#define TX_CHAIN_ADDR1_L 0x104C
+
+#ifdef BIG_ENDIAN
+typedef union _TX_CHAIN_ADDR1_L_STRUC
+{
+ struct
+ {
+ UCHAR TxChainAddr1L_Byte3; /* Destination MAC address of Tx chain1 (byte 3) */
+ UCHAR TxChainAddr1L_Byte2; /* Destination MAC address of Tx chain1 (byte 2) */
+ UCHAR TxChainAddr1L_Byte1; /* Destination MAC address of Tx chain1 (byte 1) */
+ UCHAR TxChainAddr1L_Byte0; /* Destination MAC address of Tx chain1 (byte 0) */
+ } field;
+
+ UINT32 word;
+} TX_CHAIN_ADDR1_L_STRUC, *PTX_CHAIN_ADDR1_L_STRUC;
+#else
+typedef union _TX_CHAIN_ADDR1_L_STRUC
+{
+ struct
+ {
+ UCHAR TxChainAddr1L_Byte0; /* Destination MAC address of Tx chain1 (byte 0) */
+ UCHAR TxChainAddr1L_Byte1; /* Destination MAC address of Tx chain1 (byte 1) */
+ UCHAR TxChainAddr1L_Byte2; /* Destination MAC address of Tx chain1 (byte 2) */
+ UCHAR TxChainAddr1L_Byte3; /* Destination MAC address of Tx chain1 (byte 3) */
+ } field;
+
+ UINT32 word;
+} TX_CHAIN_ADDR1_L_STRUC, *PTX_CHAIN_ADDR1_L_STRUC;
+#endif
+
+#define TX_CHAIN_ADDR1_H 0x1050
+
+#ifdef RT_BIG_ENDIAN
+typedef union _TX_CHAIN_ADDR1_H_STRUC
+{
+ struct
+ {
+ USHORT Reserved:12; /* Reserved */
+ USHORT TxChainSel0:4; /* Selection value of Tx chain0 */
+ UCHAR TxChainAddr1H_Byte5; /* Destination MAC address of Tx chain1 (byte 5) */
+ UCHAR TxChainAddr1H_Byte4; /* Destination MAC address of Tx chain1 (byte 4) */
+ } field;
+
+ UINT32 word;
+} TX_CHAIN_ADDR1_H_STRUC, *PTX_CHAIN_ADDR1_H_STRUC;
+#else
+typedef union _TX_CHAIN_ADDR1_H_STRUC
+{
+ struct
+ {
+ UCHAR TxChainAddr1H_Byte4; /* Destination MAC address of Tx chain1 (byte 4) */
+ UCHAR TxChainAddr1H_Byte5; /* Destination MAC address of Tx chain1 (byte 5) */
+ USHORT TxChainSel0:4; /* Selection value of Tx chain0 */
+ USHORT Reserved:12; /* Reserved */
+ } field;
+
+ UINT32 word;
+} TX_CHAIN_ADDR1_H_STRUC, *PTX_CHAIN_ADDR1_HA_STRUC;
+#endif
+
+#define TX_CHAIN_ADDR2_L 0x1054
+
+#ifdef RT_BIG_ENDIAN
+typedef union _TX_CHAIN_ADDR2_L_STRUC
+{
+ struct
+ {
+ UCHAR TxChainAddr2L_Byte3; /* Destination MAC address of Tx chain2 (byte 3) */
+ UCHAR TxChainAddr2L_Byte2; /* Destination MAC address of Tx chain2 (byte 2) */
+ UCHAR TxChainAddr2L_Byte1; /* Destination MAC address of Tx chain2 (byte 1) */
+ UCHAR TxChainAddr2L_Byte0; /* Destination MAC address of Tx chain2 (byte 0) */
+ } field;
+
+ UINT32 word;
+} TX_CHAIN_ADDR2_L_STRUC, *PTX_CHAIN_ADDR2_L_STRUC;
+#else
+typedef union _TX_CHAIN_ADDR2_L_STRUC
+{
+ struct
+ {
+ UCHAR TxChainAddr2L_Byte0; /* Destination MAC address of Tx chain2 (byte 0) */
+ UCHAR TxChainAddr2L_Byte1; /* Destination MAC address of Tx chain2 (byte 1) */
+ UCHAR TxChainAddr2L_Byte2; /* Destination MAC address of Tx chain2 (byte 2) */
+ UCHAR TxChainAddr2L_Byte3; /* Destination MAC address of Tx chain2 (byte 3) */
+ } field;
+
+ UINT32 word;
+} TX_CHAIN_ADDR2_L_STRUC, *PTX_CHAIN_ADDR2_L_STRUC;
+#endif
+
+#define TX_CHAIN_ADDR2_H 0x1058
+
+#ifdef RT_BIG_ENDIAN
+typedef union _TX_CHAIN_ADDR2_H_STRUC
+{
+ struct
+ {
+ USHORT Reserved:12; /* Reserved */
+ USHORT TxChainSel0:4; /* Selection value of Tx chain0 */
+ UCHAR TxChainAddr2H_Byte5; /* Destination MAC address of Tx chain2 (byte 5) */
+ UCHAR TxChainAddr2H_Byte4; /* Destination MAC address of Tx chain2 (byte 4) */
+ } field;
+
+ UINT32 word;
+} TX_CHAIN_ADDR2_H_STRUC, *PTX_CHAIN_ADDR2_H_STRUC;
+#else
+typedef union _TX_CHAIN_ADDR2_H_STRUC
+{
+ struct
+ {
+ UCHAR TxChainAddr2H_Byte4; /* Destination MAC address of Tx chain2 (byte 4) */
+ UCHAR TxChainAddr2H_Byte5; /* Destination MAC address of Tx chain2 (byte 5) */
+ USHORT TxChainSel0:4; /* Selection value of Tx chain0 */
+ USHORT Reserved:12; /* Reserved */
+ } field;
+
+ UINT32 word;
+} TX_CHAIN_ADDR2_H_STRUC, *PTX_CHAIN_ADDR2_HA_STRUC;
+#endif
+
+#define TX_CHAIN_ADDR3_L 0x105C
+
+#ifdef RT_BIG_ENDIAN
+typedef union _TX_CHAIN_ADDR3_L_STRUC
+{
+ struct
+ {
+ UCHAR TxChainAddr3L_Byte3; /* Destination MAC address of Tx chain3 (byte 3) */
+ UCHAR TxChainAddr3L_Byte2; /* Destination MAC address of Tx chain3 (byte 2) */
+ UCHAR TxChainAddr3L_Byte1; /* Destination MAC address of Tx chain3 (byte 1) */
+ UCHAR TxChainAddr3L_Byte0; /* Destination MAC address of Tx chain3 (byte 0) */
+ } field;
+
+ UINT32 word;
+} TX_CHAIN_ADDR3_L_STRUC, *PTX_CHAIN_ADDR3_L_STRUC;
+#else
+typedef union _TX_CHAIN_ADDR3_L_STRUC
+{
+ struct
+ {
+ UCHAR TxChainAddr3L_Byte0; /* Destination MAC address of Tx chain3 (byte 0) */
+ UCHAR TxChainAddr3L_Byte1; /* Destination MAC address of Tx chain3 (byte 1) */
+ UCHAR TxChainAddr3L_Byte2; /* Destination MAC address of Tx chain3 (byte 2) */
+ UCHAR TxChainAddr3L_Byte3; /* Destination MAC address of Tx chain3 (byte 3) */
+ } field;
+
+ UINT32 word;
+} TX_CHAIN_ADDR3_L_STRUC, *PTX_CHAIN_ADDR3_L_STRUC;
+#endif
+
+#define TX_CHAIN_ADDR3_H 0x1060
+
+#ifdef RT_BIG_ENDIAN
+typedef union _TX_CHAIN_ADDR3_H_STRUC
+{
+ struct
+ {
+ USHORT Reserved:12; /* Reserved */
+ USHORT TxChainSel0:4; /* Selection value of Tx chain0 */
+ UCHAR TxChainAddr3H_Byte5; /* Destination MAC address of Tx chain3 (byte 5) */
+ UCHAR TxChainAddr3H_Byte4; /* Destination MAC address of Tx chain3 (byte 4) */
+ } field;
+
+ UINT32 word;
+} TX_CHAIN_ADDR3_H_STRUC, *PTX_CHAIN_ADDR3_H_STRUC;
+#else
+typedef union _TX_CHAIN_ADDR3_H_STRUC
+{
+ struct
+ {
+ UCHAR TxChainAddr3H_Byte4; /* Destination MAC address of Tx chain3 (byte 4) */
+ UCHAR TxChainAddr3H_Byte5; /* Destination MAC address of Tx chain3 (byte 5) */
+ USHORT TxChainSel0:4; /* Selection value of Tx chain0 */
+ USHORT Reserved:12; /* Reserved */
+ } field;
+
+ UINT32 word;
+} TX_CHAIN_ADDR3_H_STRUC, *PTX_CHAIN_ADDR3_HA_STRUC;
+#endif
+
+/* */
+/* 4.2 MAC TIMING configuration registers (offset:0x1100) */
+/* */
+#define XIFS_TIME_CFG 0x1100 /* MAC_CSR8 MAC_CSR9 */
+#ifdef RT_BIG_ENDIAN
+typedef union _IFS_SLOT_CFG_STRUC {
+ struct {
+ UINT32 rsv:2;
+ UINT32 BBRxendEnable:1; /* reference RXEND signal to begin XIFS defer */
+ UINT32 EIFS:9; /* unit 1us */
+ UINT32 OfdmXifsTime:4; /*OFDM SIFS. unit 1us. Applied after OFDM RX when MAC doesn't reference BBP signal BBRXEND */
+ UINT32 OfdmSifsTime:8; /* unit 1us. Applied after OFDM RX/TX */
+ UINT32 CckmSifsTime:8; /* unit 1us. Applied after CCK RX/TX */
+ } field;
+ UINT32 word;
+} IFS_SLOT_CFG_STRUC, *PIFS_SLOT_CFG_STRUC;
+#else
+typedef union _IFS_SLOT_CFG_STRUC {
+ struct {
+ UINT32 CckmSifsTime:8; /* unit 1us. Applied after CCK RX/TX */
+ UINT32 OfdmSifsTime:8; /* unit 1us. Applied after OFDM RX/TX */
+ UINT32 OfdmXifsTime:4; /*OFDM SIFS. unit 1us. Applied after OFDM RX when MAC doesn't reference BBP signal BBRXEND */
+ UINT32 EIFS:9; /* unit 1us */
+ UINT32 BBRxendEnable:1; /* reference RXEND signal to begin XIFS defer */
+ UINT32 rsv:2;
+ } field;
+ UINT32 word;
+} IFS_SLOT_CFG_STRUC, *PIFS_SLOT_CFG_STRUC;
+#endif
+
+#define BKOFF_SLOT_CFG 0x1104 /* mac_csr9 last 8 bits */
+#define NAV_TIME_CFG 0x1108 /* NAV (MAC_CSR15) */
+#define CH_TIME_CFG 0x110C /* Count as channel busy */
+#define PBF_LIFE_TIMER 0x1110 /*TX/RX MPDU timestamp timer (free run)Unit: 1us */
+#define BCN_TIME_CFG 0x1114 /* TXRX_CSR9 */
+
+#define BCN_OFFSET0 0x042C
+#define BCN_OFFSET1 0x0430
+#ifdef SPECIFIC_BCN_BUF_SUPPORT
+#define BCN_OFFSET2 0x0444
+#define BCN_OFFSET3 0x0448
+#endif /* SPECIFIC_BCN_BUF_SUPPORT */
+
+/* */
+/* BCN_TIME_CFG : Synchronization control register */
+/* */
+#ifdef RT_BIG_ENDIAN
+typedef union _BCN_TIME_CFG_STRUC {
+ struct {
+ UINT32 TxTimestampCompensate:8;
+ UINT32 :3;
+ UINT32 bBeaconGen:1; /* Enable beacon generator */
+ UINT32 bTBTTEnable:1;
+ UINT32 TsfSyncMode:2; /* Enable TSF sync, 00: disable, 01: infra mode, 10: ad-hoc mode */
+ UINT32 bTsfTicking:1; /* Enable TSF auto counting */
+ UINT32 BeaconInterval:16; /* in unit of 1/16 TU */
+ } field;
+ UINT32 word;
+} BCN_TIME_CFG_STRUC, *PBCN_TIME_CFG_STRUC;
+#else
+typedef union _BCN_TIME_CFG_STRUC {
+ struct {
+ UINT32 BeaconInterval:16; /* in unit of 1/16 TU */
+ UINT32 bTsfTicking:1; /* Enable TSF auto counting */
+ UINT32 TsfSyncMode:2; /* Enable TSF sync, 00: disable, 01: infra mode, 10: ad-hoc mode */
+ UINT32 bTBTTEnable:1;
+ UINT32 bBeaconGen:1; /* Enable beacon generator */
+ UINT32 :3;
+ UINT32 TxTimestampCompensate:8;
+ } field;
+ UINT32 word;
+} BCN_TIME_CFG_STRUC, *PBCN_TIME_CFG_STRUC;
+#endif
+#define TBTT_SYNC_CFG 0x1118 /* txrx_csr10 */
+#define TSF_TIMER_DW0 0x111C /* Local TSF timer lsb 32 bits. Read-only */
+#define TSF_TIMER_DW1 0x1120 /* msb 32 bits. Read-only. */
+#define TBTT_TIMER 0x1124 /* TImer remains till next TBTT. Read-only. TXRX_CSR14 */
+#define INT_TIMER_CFG 0x1128 /* */
+#define INT_TIMER_EN 0x112c /* GP-timer and pre-tbtt Int enable */
+#define CH_IDLE_STA 0x1130 /* channel idle time */
+#define CH_BUSY_STA 0x1134 /* channle busy time */
+#define CH_BUSY_STA_SEC 0x1138 /* channel busy time for secondary channel */
+/* */
+/* 4.2 MAC POWER configuration registers (offset:0x1200) */
+/* */
+#define MAC_STATUS_CFG 0x1200 /* old MAC_CSR12 */
+#define PWR_PIN_CFG 0x1204 /* old MAC_CSR12 */
+#define AUTO_WAKEUP_CFG 0x1208 /* old MAC_CSR10 */
+/* */
+/* AUTO_WAKEUP_CFG: Manual power control / status register */
+/* */
+#ifdef RT_BIG_ENDIAN
+typedef union _AUTO_WAKEUP_STRUC {
+ struct {
+ UINT32 :16;
+ UINT32 EnableAutoWakeup:1; /* 0:sleep, 1:awake */
+ UINT32 NumofSleepingTbtt:7; /* ForceWake has high privilege than PutToSleep when both set */
+ UINT32 AutoLeadTime:8;
+ } field;
+ UINT32 word;
+} AUTO_WAKEUP_STRUC, *PAUTO_WAKEUP_STRUC;
+#else
+typedef union _AUTO_WAKEUP_STRUC {
+ struct {
+ UINT32 AutoLeadTime:8;
+ UINT32 NumofSleepingTbtt:7; /* ForceWake has high privilege than PutToSleep when both set */
+ UINT32 EnableAutoWakeup:1; /* 0:sleep, 1:awake */
+ UINT32 :16;
+ } field;
+ UINT32 word;
+} AUTO_WAKEUP_STRUC, *PAUTO_WAKEUP_STRUC;
+#endif
+/* */
+/* 4.3 MAC TX configuration registers (offset:0x1300) */
+/* */
+
+#define EDCA_AC0_CFG 0x1300 /*AC_TXOP_CSR0 0x3474 */
+#define EDCA_AC1_CFG 0x1304
+#define EDCA_AC2_CFG 0x1308
+#define EDCA_AC3_CFG 0x130c
+#ifdef RT_BIG_ENDIAN
+typedef union _EDCA_AC_CFG_STRUC {
+ struct {
+ UINT32 :12; /* */
+ UINT32 Cwmax:4; /*unit power of 2 */
+ UINT32 Cwmin:4; /* */
+ UINT32 Aifsn:4; /* # of slot time */
+ UINT32 AcTxop:8; /* in unit of 32us */
+ } field;
+ UINT32 word;
+} EDCA_AC_CFG_STRUC, *PEDCA_AC_CFG_STRUC;
+#else
+typedef union _EDCA_AC_CFG_STRUC {
+ struct {
+ UINT32 AcTxop:8; /* in unit of 32us */
+ UINT32 Aifsn:4; /* # of slot time */
+ UINT32 Cwmin:4; /* */
+ UINT32 Cwmax:4; /*unit power of 2 */
+ UINT32 :12; /* */
+ } field;
+ UINT32 word;
+} EDCA_AC_CFG_STRUC, *PEDCA_AC_CFG_STRUC;
+#endif
+
+/* */
+/* Default Tx power */
+/* */
+#define DEFAULT_TX_POWER 0x6
+
+#define EDCA_TID_AC_MAP 0x1310
+#define TX_PWR_CFG_0 0x1314
+#define TX_PWR_CFG_0_EXT 0x1390
+#define TX_PWR_CFG_1 0x1318
+#define TX_PWR_CFG_1_EXT 0x1394
+#define TX_PWR_CFG_2 0x131C
+#define TX_PWR_CFG_2_EXT 0x1398
+#define TX_PWR_CFG_3 0x1320
+#define TX_PWR_CFG_3_EXT 0x139C
+#define TX_PWR_CFG_4 0x1324
+#define TX_PWR_CFG_4_EXT 0x13A0
+#define TX_PWR_CFG_5 0x1384
+#define TX_PWR_CFG_6 0x1388
+#define TX_PWR_CFG_7 0x13D4
+#define TX_PWR_CFG_8 0x13D8
+#define TX_PWR_CFG_9 0x13DC
+
+#ifdef RT_BIG_ENDIAN
+typedef union _TX_PWR_CFG_STRUC {
+ struct {
+ ULONG Byte3:8;
+ ULONG Byte2:8;
+ ULONG Byte1:8;
+ ULONG Byte0:8;
+ } field;
+ ULONG word;
+} TX_PWR_CFG_STRUC, *PTX_PWR_CFG_STRUC;
+#else
+typedef union _TX_PWR_CFG_STRUC {
+ struct {
+ ULONG Byte0:8;
+ ULONG Byte1:8;
+ ULONG Byte2:8;
+ ULONG Byte3:8;
+ } field;
+ ULONG word;
+} TX_PWR_CFG_STRUC, *PTX_PWR_CFG_STRUC;
+#endif
+
+#define TX_PIN_CFG 0x1328
+#define TX_BAND_CFG 0x132c /* 0x1 use upper 20MHz. 0 juse lower 20MHz */
+#define TX_SW_CFG0 0x1330
+#define TX_SW_CFG1 0x1334
+#define TX_SW_CFG2 0x1338
+#define TXOP_THRES_CFG 0x133c
+
+#ifdef RT_BIG_ENDIAN
+typedef union _TXOP_THRESHOLD_CFG_STRUC
+{
+ struct
+ {
+ UINT32 TXOP_REM_THRES:8; /* Remaining TXOP threshold (unit: 32us) */
+ UINT32 CF_END_THRES:8; /* CF-END threshold (unit: 32us) */
+ UINT32 RDG_IN_THRES:8; /* Rx RDG threshold (unit: 32us) */
+ UINT32 RDG_OUT_THRES:8; /* Tx RDG threshold (unit: 32us) */
+ } field;
+
+ UINT32 word;
+} TXOP_THRESHOLD_CFG_STRUC, *PTXOP_THRESHOLD_CFG_STRUC;
+#else
+typedef union _TXOP_THRESHOLD_CFG_STRUC
+{
+ struct
+ {
+ UINT32 RDG_OUT_THRES:8; /* Tx RDG threshold (unit: 32us) */
+ UINT32 RDG_IN_THRES:8; /* Rx RDG threshold (unit: 32us) */
+ UINT32 CF_END_THRES:8; /* CF-END threshold (unit: 32us) */
+ UINT32 TXOP_REM_THRES:8; /* Remaining TXOP threshold (unit: 32us) */
+ } field;
+
+ UINT32 word;
+} TXOP_THRESHOLD_CFG_STRUC, *PTXOP_THRESHOLD_CFG_STRUC;
+#endif
+
+#define TXOP_CTRL_CFG 0x1340
+#define TX_RTS_CFG 0x1344
+
+#define TX_TXBF_CFG_0 0x138c
+#define TX_TXBF_CFG_1 0x13A4
+#define TX_TXBF_CFG_2 0x13A8
+#define TX_TXBF_CFG_3 0x13AC
+
+#ifdef RT_BIG_ENDIAN
+typedef union _TX_RTS_CFG_STRUC {
+ struct {
+ UINT32 rsv:7;
+ UINT32 RtsFbkEn:1; /* enable rts rate fallback */
+ UINT32 RtsThres:16; /* unit:byte */
+ UINT32 AutoRtsRetryLimit:8;
+ } field;
+ UINT32 word;
+} TX_RTS_CFG_STRUC, *PTX_RTS_CFG_STRUC;
+#else
+typedef union _TX_RTS_CFG_STRUC {
+ struct {
+ UINT32 AutoRtsRetryLimit:8;
+ UINT32 RtsThres:16; /* unit:byte */
+ UINT32 RtsFbkEn:1; /* enable rts rate fallback */
+ UINT32 rsv:7; /* 1: HT non-STBC control frame enable */
+ } field;
+ UINT32 word;
+} TX_RTS_CFG_STRUC, *PTX_RTS_CFG_STRUC;
+#endif
+
+typedef union _TX_TXBF_CFG_0_STRUC {
+ struct {
+#ifdef RT_BIG_ENDIAN
+ UINT32 EtxbfFbkRate:16;
+ UINT32 EtxbfFbkEn:1;
+ UINT32 EtxbfFbkSeqEn:1;
+ UINT32 EtxbfFbkCoef:2;
+ UINT32 EtxbfFbkCode:2;
+ UINT32 EtxbfFbkNg:2;
+ UINT32 CsdBypass:1;
+ UINT32 EtxbfForce:1;
+ UINT32 EtxbfEnable:1;
+ UINT32 AutoTxbfEn:3;
+ UINT32 ItxbfForce:1;
+ UINT32 ItxbfEn:1;
+#else
+ UINT32 ItxbfEn:1;
+ UINT32 ItxbfForce:1;
+ UINT32 AutoTxbfEn:3;
+ UINT32 EtxbfEnable:1;
+ UINT32 EtxbfForce:1;
+ UINT32 CsdBypass:1;
+ UINT32 EtxbfFbkNg:2;
+ UINT32 EtxbfFbkCode:2;
+ UINT32 EtxbfFbkCoef:2;
+ UINT32 EtxbfFbkSeqEn:1;
+ UINT32 EtxbfFbkEn:1;
+ UINT32 EtxbfFbkRate:16;
+#endif
+ } field;
+ UINT32 word;
+} TX_TXBF_CFG_0_STRUC, *PTX_TXBF_CFG_0_STRUC;
+
+#define TX_TIMEOUT_CFG 0x1348
+#ifdef RT_BIG_ENDIAN
+typedef union _TX_TIMEOUT_CFG_STRUC {
+ struct {
+ UINT32 rsv2:8;
+ UINT32 TxopTimeout:8; /*TXOP timeout value for TXOP truncation. It is recommended that (SLOT_TIME) > (TX_OP_TIMEOUT) > (RX_ACK_TIMEOUT) */
+ UINT32 RxAckTimeout:8; /* unit:slot. Used for TX precedure */
+ UINT32 MpduLifeTime:4; /* expiration time = 2^(9+MPDU LIFE TIME) us */
+ UINT32 rsv:4;
+ } field;
+ UINT32 word;
+} TX_TIMEOUT_CFG_STRUC, *PTX_TIMEOUT_CFG_STRUC;
+#else
+typedef union _TX_TIMEOUT_CFG_STRUC {
+ struct {
+ UINT32 rsv:4;
+ UINT32 MpduLifeTime:4; /* expiration time = 2^(9+MPDU LIFE TIME) us */
+ UINT32 RxAckTimeout:8; /* unit:slot. Used for TX precedure */
+ UINT32 TxopTimeout:8; /*TXOP timeout value for TXOP truncation. It is recommended that (SLOT_TIME) > (TX_OP_TIMEOUT) > (RX_ACK_TIMEOUT) */
+ UINT32 rsv2:8; /* 1: HT non-STBC control frame enable */
+ } field;
+ UINT32 word;
+} TX_TIMEOUT_CFG_STRUC, *PTX_TIMEOUT_CFG_STRUC;
+#endif
+
+#define TX_RTY_CFG 0x134c
+#define TX_AC_RTY_LIMIT 0x13cc
+#define TX_AC_FBK_SPEED 0x13d0
+
+#ifdef RT_BIG_ENDIAN
+typedef union GNU_PACKED _TX_RTY_CFG_STRUC {
+ struct {
+ UINT32 rsv:1;
+ UINT32 TxautoFBEnable:1; /* Tx retry PHY rate auto fallback enable */
+ UINT32 AggRtyMode:1; /* Aggregate MPDU retry mode. 0:expired by retry limit, 1: expired by mpdu life timer */
+ UINT32 NonAggRtyMode:1; /* Non-Aggregate MPDU retry mode. 0:expired by retry limit, 1: expired by mpdu life timer */
+ UINT32 LongRtyThre:12; /* Long retry threshoold */
+ UINT32 LongRtyLimit:8; /*long retry limit */
+ UINT32 ShortRtyLimit:8; /* short retry limit */
+
+ } field;
+ UINT32 word;
+} TX_RTY_CFG_STRUC, *PTX_RTY_CFG_STRUC;
+#else
+typedef union GNU_PACKED _TX_RTY_CFG_STRUC {
+ struct {
+ UINT32 ShortRtyLimit:8; /* short retry limit */
+ UINT32 LongRtyLimit:8; /*long retry limit */
+ UINT32 LongRtyThre:12; /* Long retry threshoold */
+ UINT32 NonAggRtyMode:1; /* Non-Aggregate MPDU retry mode. 0:expired by retry limit, 1: expired by mpdu life timer */
+ UINT32 AggRtyMode:1; /* Aggregate MPDU retry mode. 0:expired by retry limit, 1: expired by mpdu life timer */
+ UINT32 TxautoFBEnable:1; /* Tx retry PHY rate auto fallback enable */
+ UINT32 rsv:1; /* 1: HT non-STBC control frame enable */
+ } field;
+ UINT32 word;
+} TX_RTY_CFG_STRUC, *PTX_RTY_CFG_STRUC;
+#endif
+#define TX_LINK_CFG 0x1350
+#ifdef RT_BIG_ENDIAN
+typedef union GNU_PACKED _TX_LINK_CFG_STRUC {
+ struct GNU_PACKED {
+ UINT32 RemotMFS:8; /*remote MCS feedback sequence number */
+ UINT32 RemotMFB:8; /* remote MCS feedback */
+ UINT32 rsv:3; /* */
+ UINT32 TxCFAckEn:1; /* Piggyback CF-ACK enable */
+ UINT32 TxRDGEn:1; /* RDG TX enable */
+ UINT32 TxMRQEn:1; /* MCS request TX enable */
+ UINT32 RemoteUMFSEnable:1; /* remote unsolicit MFB enable. 0: not apply remote remote unsolicit (MFS=7) */
+ UINT32 MFBEnable:1; /* TX apply remote MFB 1:enable */
+ UINT32 RemoteMFBLifeTime:8; /*remote MFB life time. unit : 32us */
+ } field;
+ UINT32 word;
+} TX_LINK_CFG_STRUC, *PTX_LINK_CFG_STRUC;
+#else
+typedef union GNU_PACKED _TX_LINK_CFG_STRUC {
+ struct GNU_PACKED {
+ UINT32 RemoteMFBLifeTime:8; /*remote MFB life time. unit : 32us */
+ UINT32 MFBEnable:1; /* TX apply remote MFB 1:enable */
+ UINT32 RemoteUMFSEnable:1; /* remote unsolicit MFB enable. 0: not apply remote remote unsolicit (MFS=7) */
+ UINT32 TxMRQEn:1; /* MCS request TX enable */
+ UINT32 TxRDGEn:1; /* RDG TX enable */
+ UINT32 TxCFAckEn:1; /* Piggyback CF-ACK enable */
+ UINT32 rsv:3; /* */
+ UINT32 RemotMFB:8; /* remote MCS feedback */
+ UINT32 RemotMFS:8; /*remote MCS feedback sequence number */
+ } field;
+ UINT32 word;
+} TX_LINK_CFG_STRUC, *PTX_LINK_CFG_STRUC;
+#endif
+#define HT_FBK_CFG0 0x1354
+#ifdef RT_BIG_ENDIAN
+typedef union GNU_PACKED _HT_FBK_CFG0_STRUC {
+ struct {
+ UINT32 HTMCS7FBK:4;
+ UINT32 HTMCS6FBK:4;
+ UINT32 HTMCS5FBK:4;
+ UINT32 HTMCS4FBK:4;
+ UINT32 HTMCS3FBK:4;
+ UINT32 HTMCS2FBK:4;
+ UINT32 HTMCS1FBK:4;
+ UINT32 HTMCS0FBK:4;
+ } field;
+ UINT32 word;
+} HT_FBK_CFG0_STRUC, *PHT_FBK_CFG0_STRUC;
+#else
+typedef union GNU_PACKED _HT_FBK_CFG0_STRUC {
+ struct {
+ UINT32 HTMCS0FBK:4;
+ UINT32 HTMCS1FBK:4;
+ UINT32 HTMCS2FBK:4;
+ UINT32 HTMCS3FBK:4;
+ UINT32 HTMCS4FBK:4;
+ UINT32 HTMCS5FBK:4;
+ UINT32 HTMCS6FBK:4;
+ UINT32 HTMCS7FBK:4;
+ } field;
+ UINT32 word;
+} HT_FBK_CFG0_STRUC, *PHT_FBK_CFG0_STRUC;
+#endif
+#define HT_FBK_CFG1 0x1358
+#ifdef RT_BIG_ENDIAN
+typedef union _HT_FBK_CFG1_STRUC {
+ struct {
+ UINT32 HTMCS15FBK:4;
+ UINT32 HTMCS14FBK:4;
+ UINT32 HTMCS13FBK:4;
+ UINT32 HTMCS12FBK:4;
+ UINT32 HTMCS11FBK:4;
+ UINT32 HTMCS10FBK:4;
+ UINT32 HTMCS9FBK:4;
+ UINT32 HTMCS8FBK:4;
+ } field;
+ UINT32 word;
+} HT_FBK_CFG1_STRUC, *PHT_FBK_CFG1_STRUC;
+#else
+typedef union _HT_FBK_CFG1_STRUC {
+ struct {
+ UINT32 HTMCS8FBK:4;
+ UINT32 HTMCS9FBK:4;
+ UINT32 HTMCS10FBK:4;
+ UINT32 HTMCS11FBK:4;
+ UINT32 HTMCS12FBK:4;
+ UINT32 HTMCS13FBK:4;
+ UINT32 HTMCS14FBK:4;
+ UINT32 HTMCS15FBK:4;
+ } field;
+ UINT32 word;
+} HT_FBK_CFG1_STRUC, *PHT_FBK_CFG1_STRUC;
+#endif
+#define LG_FBK_CFG0 0x135c
+#ifdef RT_BIG_ENDIAN
+typedef union _LG_FBK_CFG0_STRUC {
+ struct {
+ UINT32 OFDMMCS7FBK:4; /*initial value is 6 */
+ UINT32 OFDMMCS6FBK:4; /*initial value is 5 */
+ UINT32 OFDMMCS5FBK:4; /*initial value is 4 */
+ UINT32 OFDMMCS4FBK:4; /*initial value is 3 */
+ UINT32 OFDMMCS3FBK:4; /*initial value is 2 */
+ UINT32 OFDMMCS2FBK:4; /*initial value is 1 */
+ UINT32 OFDMMCS1FBK:4; /*initial value is 0 */
+ UINT32 OFDMMCS0FBK:4; /*initial value is 0 */
+ } field;
+ UINT32 word;
+} LG_FBK_CFG0_STRUC, *PLG_FBK_CFG0_STRUC;
+#else
+typedef union _LG_FBK_CFG0_STRUC {
+ struct {
+ UINT32 OFDMMCS0FBK:4; /*initial value is 0 */
+ UINT32 OFDMMCS1FBK:4; /*initial value is 0 */
+ UINT32 OFDMMCS2FBK:4; /*initial value is 1 */
+ UINT32 OFDMMCS3FBK:4; /*initial value is 2 */
+ UINT32 OFDMMCS4FBK:4; /*initial value is 3 */
+ UINT32 OFDMMCS5FBK:4; /*initial value is 4 */
+ UINT32 OFDMMCS6FBK:4; /*initial value is 5 */
+ UINT32 OFDMMCS7FBK:4; /*initial value is 6 */
+ } field;
+ UINT32 word;
+} LG_FBK_CFG0_STRUC, *PLG_FBK_CFG0_STRUC;
+#endif
+#define LG_FBK_CFG1 0x1360
+#ifdef RT_BIG_ENDIAN
+typedef union _LG_FBK_CFG1_STRUC {
+ struct {
+ UINT32 rsv:16;
+ UINT32 CCKMCS3FBK:4; /*initial value is 2 */
+ UINT32 CCKMCS2FBK:4; /*initial value is 1 */
+ UINT32 CCKMCS1FBK:4; /*initial value is 0 */
+ UINT32 CCKMCS0FBK:4; /*initial value is 0 */
+ } field;
+ UINT32 word;
+} LG_FBK_CFG1_STRUC, *PLG_FBK_CFG1_STRUC;
+#else
+typedef union _LG_FBK_CFG1_STRUC {
+ struct {
+ UINT32 CCKMCS0FBK:4; /*initial value is 0 */
+ UINT32 CCKMCS1FBK:4; /*initial value is 0 */
+ UINT32 CCKMCS2FBK:4; /*initial value is 1 */
+ UINT32 CCKMCS3FBK:4; /*initial value is 2 */
+ UINT32 rsv:16;
+ } field;
+ UINT32 word;
+} LG_FBK_CFG1_STRUC, *PLG_FBK_CFG1_STRUC;
+#endif
+
+#ifdef DOT11N_SS3_SUPPORT
+#define TX_FBK_CFG_3S_0 0x13c4
+#ifdef RT_BIG_ENDIAN
+typedef union _TX_FBK_CFG_3S_0_STRUC {
+ struct {
+ UINT32 rsv0:3;
+ UINT32 HTMCS19FBK:5;
+ UINT32 rsv1:3;
+ UINT32 HTMCS18FBK:5;
+ UINT32 rsv2:3;
+ UINT32 HTMCS17FBK:5;
+ UINT32 rsv3:3;
+ UINT32 HTMCS16FBK:5;
+ } field;
+ UINT32 word;
+} TX_FBK_CFG_3S_0_STRUC, *PTX_FBK_CFG_3S_0_STRUC;
+#else
+typedef union _TX_FBK_CFG_3S_0_STRUC {
+ struct {
+ UINT32 HTMCS16FBK:5;
+ UINT32 rsv3:3;
+ UINT32 HTMCS17FBK:5;
+ UINT32 rsv2:3;
+ UINT32 HTMCS18FBK:5;
+ UINT32 rsv1:3;
+ UINT32 HTMCS19FBK:5;
+ UINT32 rsv0:4;
+ } field;
+ UINT32 word;
+} TX_FBK_CFG_3S_0_STRUC, *PTX_FBK_CFG_3S_0_STRUC;
+#endif
+
+#define TX_FBK_CFG_3S_1 0x13c8
+#ifdef RT_BIG_ENDIAN
+typedef union _TX_FBK_CFG_3S_1_STRUC {
+ struct {
+ UINT32 rsv0:3;
+ UINT32 HTMCS23FBK:5;
+ UINT32 rsv1:3;
+ UINT32 HTMCS22FBK:5;
+ UINT32 rsv2:3;
+ UINT32 HTMCS21FBK:5;
+ UINT32 rsv3:3;
+ UINT32 HTMCS20FBK:5;
+ } field;
+ UINT32 word;
+} TX_FBK_CFG_3S_1_STRUC, *PTX_FBK_CFG_3S_1_STRUC;
+#else
+typedef union _TX_FBK_CFG_3S_1_STRUC {
+ struct {
+ UINT32 HTMCS20FBK:5;
+ UINT32 rsv3:3;
+ UINT32 HTMCS21FBK:5;
+ UINT32 rsv2:3;
+ UINT32 HTMCS22FBK:5;
+ UINT32 rsv1:3;
+ UINT32 HTMCS23FBK:5;
+ UINT32 rsv0:3;
+ } field;
+ UINT32 word;
+} TX_FBK_CFG_3S_1_STRUC, *PTX_FBK_CFG_3S_1_STRUC;
+#endif
+#endif /* DOT11N_SS3_SUPPORT */
+
+/*======================================================= */
+/*================ Protection Paramater================================ */
+/*======================================================= */
+#define CCK_PROT_CFG 0x1364 /*CCK Protection */
+#define ASIC_SHORTNAV 1
+#define ASIC_LONGNAV 2
+#define ASIC_RTS 1
+#define ASIC_CTS 2
+#ifdef RT_BIG_ENDIAN
+typedef union _PROT_CFG_STRUC {
+ struct {
+ UINT32 rsv:5;
+ UINT32 RTSThEn:1; /*RTS threshold enable on CCK TX */
+ UINT32 TxopAllowGF40:1; /*CCK TXOP allowance.0:disallow. */
+ UINT32 TxopAllowGF20:1; /*CCK TXOP allowance.0:disallow. */
+ UINT32 TxopAllowMM40:1; /*CCK TXOP allowance.0:disallow. */
+ UINT32 TxopAllowMM20:1; /*CCK TXOP allowance. 0:disallow. */
+ UINT32 TxopAllowOfdm:1; /*CCK TXOP allowance.0:disallow. */
+ UINT32 TxopAllowCck:1; /*CCK TXOP allowance.0:disallow. */
+ UINT32 ProtectNav:2; /*TXOP protection type for CCK TX. 0:None, 1:ShortNAVprotect, 2:LongNAVProtect, 3:rsv */
+ UINT32 ProtectCtrl:2; /*Protection control frame type for CCK TX. 1:RTS/CTS, 2:CTS-to-self, 0:None, 3:rsv */
+ UINT32 ProtectRate:16; /*Protection control frame rate for CCK TX(RTS/CTS/CFEnd). */
+ } field;
+ UINT32 word;
+} PROT_CFG_STRUC, *PPROT_CFG_STRUC;
+#else
+typedef union _PROT_CFG_STRUC {
+ struct {
+ UINT32 ProtectRate:16; /*Protection control frame rate for CCK TX(RTS/CTS/CFEnd). */
+ UINT32 ProtectCtrl:2; /*Protection control frame type for CCK TX. 1:RTS/CTS, 2:CTS-to-self, 0:None, 3:rsv */
+ UINT32 ProtectNav:2; /*TXOP protection type for CCK TX. 0:None, 1:ShortNAVprotect, 2:LongNAVProtect, 3:rsv */
+ UINT32 TxopAllowCck:1; /*CCK TXOP allowance.0:disallow. */
+ UINT32 TxopAllowOfdm:1; /*CCK TXOP allowance.0:disallow. */
+ UINT32 TxopAllowMM20:1; /*CCK TXOP allowance. 0:disallow. */
+ UINT32 TxopAllowMM40:1; /*CCK TXOP allowance.0:disallow. */
+ UINT32 TxopAllowGF20:1; /*CCK TXOP allowance.0:disallow. */
+ UINT32 TxopAllowGF40:1; /*CCK TXOP allowance.0:disallow. */
+ UINT32 RTSThEn:1; /*RTS threshold enable on CCK TX */
+ UINT32 rsv:5;
+ } field;
+ UINT32 word;
+} PROT_CFG_STRUC, *PPROT_CFG_STRUC;
+#endif
+
+#define OFDM_PROT_CFG 0x1368 /*OFDM Protection */
+#define MM20_PROT_CFG 0x136C /*MM20 Protection */
+#define MM40_PROT_CFG 0x1370 /*MM40 Protection */
+#define GF20_PROT_CFG 0x1374 /*GF20 Protection */
+#define GF40_PROT_CFG 0x1378 /*GR40 Protection */
+#define EXP_CTS_TIME 0x137C /* */
+#define EXP_ACK_TIME 0x1380 /* */
+
+
+/* */
+/* 4.4 MAC RX configuration registers (offset:0x1400) */
+/* */
+#define RX_FILTR_CFG 0x1400 /*TXRX_CSR0 */
+#define AUTO_RSP_CFG 0x1404 /*TXRX_CSR4 */
+/* */
+/* TXRX_CSR4: Auto-Responder/ */
+/* */
+#ifdef RT_BIG_ENDIAN
+typedef union _AUTO_RSP_CFG_STRUC {
+ struct {
+ UINT32 :24;
+ UINT32 AckCtsPsmBit:1; /* Power bit value in conrtrol frame */
+ UINT32 DualCTSEn:1; /* Power bit value in conrtrol frame */
+ UINT32 rsv:1; /* Power bit value in conrtrol frame */
+ UINT32 AutoResponderPreamble:1; /* 0:long, 1:short preamble */
+ UINT32 CTS40MRef:1; /* Response CTS 40MHz duplicate mode */
+ UINT32 CTS40MMode:1; /* Response CTS 40MHz duplicate mode */
+ UINT32 BACAckPolicyEnable:1; /* 0:long, 1:short preamble */
+ UINT32 AutoResponderEnable:1;
+ } field;
+ UINT32 word;
+} AUTO_RSP_CFG_STRUC, *PAUTO_RSP_CFG_STRUC;
+#else
+typedef union _AUTO_RSP_CFG_STRUC {
+ struct {
+ UINT32 AutoResponderEnable:1;
+ UINT32 BACAckPolicyEnable:1; /* 0:long, 1:short preamble */
+ UINT32 CTS40MMode:1; /* Response CTS 40MHz duplicate mode */
+ UINT32 CTS40MRef:1; /* Response CTS 40MHz duplicate mode */
+ UINT32 AutoResponderPreamble:1; /* 0:long, 1:short preamble */
+ UINT32 rsv:1; /* Power bit value in conrtrol frame */
+ UINT32 DualCTSEn:1; /* Power bit value in conrtrol frame */
+ UINT32 AckCtsPsmBit:1; /* Power bit value in conrtrol frame */
+ UINT32 :24;
+ } field;
+ UINT32 word;
+} AUTO_RSP_CFG_STRUC, *PAUTO_RSP_CFG_STRUC;
+#endif
+
+#define LEGACY_BASIC_RATE 0x1408 /* TXRX_CSR5 0x3054 */
+#define HT_BASIC_RATE 0x140c
+#define HT_CTRL_CFG 0x1410
+#define SIFS_COST_CFG 0x1414
+#define RX_PARSER_CFG 0x1418 /*Set NAV for all received frames */
+
+/* */
+/* 4.5 MAC Security configuration (offset:0x1500) */
+/* */
+#define TX_SEC_CNT0 0x1500 /* */
+#define RX_SEC_CNT0 0x1504 /* */
+#define CCMP_FC_MUTE 0x1508 /* */
+/* */
+/* 4.6 HCCA/PSMP (offset:0x1600) */
+/* */
+#define TXOP_HLDR_ADDR0 0x1600
+#define TXOP_HLDR_ADDR1 0x1604
+#define TXOP_HLDR_ET 0x1608
+#define QOS_CFPOLL_RA_DW0 0x160c
+#define QOS_CFPOLL_A1_DW1 0x1610
+#define QOS_CFPOLL_QC 0x1614
+/* */
+/* 4.7 MAC Statistis registers (offset:0x1700) */
+/* */
+#define RX_STA_CNT0 0x1700 /* */
+#define RX_STA_CNT1 0x1704 /* */
+#define RX_STA_CNT2 0x1708 /* */
+
+/* */
+/* RX_STA_CNT0_STRUC: RX PLCP error count & RX CRC error count */
+/* */
+#ifdef RT_BIG_ENDIAN
+typedef union _RX_STA_CNT0_STRUC {
+ struct {
+ USHORT PhyErr;
+ USHORT CrcErr;
+ } field;
+ UINT32 word;
+} RX_STA_CNT0_STRUC, *PRX_STA_CNT0_STRUC;
+#else
+typedef union _RX_STA_CNT0_STRUC {
+ struct {
+ USHORT CrcErr;
+ USHORT PhyErr;
+ } field;
+ UINT32 word;
+} RX_STA_CNT0_STRUC, *PRX_STA_CNT0_STRUC;
+#endif
+
+/* */
+/* RX_STA_CNT1_STRUC: RX False CCA count & RX LONG frame count */
+/* */
+#ifdef RT_BIG_ENDIAN
+typedef union _RX_STA_CNT1_STRUC {
+ struct {
+ USHORT PlcpErr;
+ USHORT FalseCca;
+ } field;
+ UINT32 word;
+} RX_STA_CNT1_STRUC, *PRX_STA_CNT1_STRUC;
+#else
+typedef union _RX_STA_CNT1_STRUC {
+ struct {
+ USHORT FalseCca;
+ USHORT PlcpErr;
+ } field;
+ UINT32 word;
+} RX_STA_CNT1_STRUC, *PRX_STA_CNT1_STRUC;
+#endif
+
+/* */
+/* RX_STA_CNT2_STRUC: */
+/* */
+#ifdef RT_BIG_ENDIAN
+typedef union _RX_STA_CNT2_STRUC {
+ struct {
+ USHORT RxFifoOverflowCount;
+ USHORT RxDupliCount;
+ } field;
+ UINT32 word;
+} RX_STA_CNT2_STRUC, *PRX_STA_CNT2_STRUC;
+#else
+typedef union _RX_STA_CNT2_STRUC {
+ struct {
+ USHORT RxDupliCount;
+ USHORT RxFifoOverflowCount;
+ } field;
+ UINT32 word;
+} RX_STA_CNT2_STRUC, *PRX_STA_CNT2_STRUC;
+#endif
+#define TX_STA_CNT0 0x170C /* */
+/* */
+/* STA_CSR3: TX Beacon count */
+/* */
+#ifdef RT_BIG_ENDIAN
+typedef union _TX_STA_CNT0_STRUC {
+ struct {
+ USHORT TxBeaconCount;
+ USHORT TxFailCount;
+ } field;
+ UINT32 word;
+} TX_STA_CNT0_STRUC, *PTX_STA_CNT0_STRUC;
+#else
+typedef union _TX_STA_CNT0_STRUC {
+ struct {
+ USHORT TxFailCount;
+ USHORT TxBeaconCount;
+ } field;
+ UINT32 word;
+} TX_STA_CNT0_STRUC, *PTX_STA_CNT0_STRUC;
+#endif
+#define TX_STA_CNT1 0x1710 /* */
+/* */
+/* TX_STA_CNT1: TX tx count */
+/* */
+#ifdef RT_BIG_ENDIAN
+typedef union _TX_STA_CNT1_STRUC {
+ struct {
+ USHORT TxRetransmit;
+ USHORT TxSuccess;
+ } field;
+ UINT32 word;
+} TX_STA_CNT1_STRUC, *PTX_STA_CNT1_STRUC;
+#else
+typedef union _TX_STA_CNT1_STRUC {
+ struct {
+ USHORT TxSuccess;
+ USHORT TxRetransmit;
+ } field;
+ UINT32 word;
+} TX_STA_CNT1_STRUC, *PTX_STA_CNT1_STRUC;
+#endif
+#define TX_STA_CNT2 0x1714 /* */
+/* */
+/* TX_STA_CNT2: TX tx count */
+/* */
+#ifdef RT_BIG_ENDIAN
+typedef union _TX_STA_CNT2_STRUC {
+ struct {
+ USHORT TxUnderFlowCount;
+ USHORT TxZeroLenCount;
+ } field;
+ UINT32 word;
+} TX_STA_CNT2_STRUC, *PTX_STA_CNT2_STRUC;
+#else
+typedef union _TX_STA_CNT2_STRUC {
+ struct {
+ USHORT TxZeroLenCount;
+ USHORT TxUnderFlowCount;
+ } field;
+ UINT32 word;
+} TX_STA_CNT2_STRUC, *PTX_STA_CNT2_STRUC;
+#endif
+#define TX_STA_FIFO 0x1718 /* */
+/* */
+/* TX_STA_FIFO_STRUC: TX Result for specific PID status fifo register */
+/* */
+#ifdef RT_BIG_ENDIAN
+typedef union GNU_PACKED _TX_STA_FIFO_STRUC {
+ struct {
+ UINT32 Reserve:2;
+ UINT32 iTxBF:1; /* iTxBF enable */
+ UINT32 Sounding:1; /* Sounding enable */
+ UINT32 eTxBF:1; /* eTxBF enable */
+ UINT32 SuccessRate:11; /*include MCS, mode ,shortGI, BW settingSame format as TXWI Word 0 Bit 31-16. */
+ UINT32 wcid:8; /*wireless client index */
+ UINT32 TxAckRequired:1; /* ack required */
+ UINT32 TxAggre:1; /* Tx is aggregated */
+ UINT32 TxSuccess:1; /* Tx success. whether success or not */
+ UINT32 PidType:4;
+ UINT32 bValid:1; /* 1:This register contains a valid TX result */
+ } field;
+ UINT32 word;
+} TX_STA_FIFO_STRUC, *PTX_STA_FIFO_STRUC;
+#else
+typedef union GNU_PACKED _TX_STA_FIFO_STRUC {
+ struct {
+ UINT32 bValid:1; /* 1:This register contains a valid TX result */
+ UINT32 PidType:4;
+ UINT32 TxSuccess:1; /* Tx No retry success */
+ UINT32 TxAggre:1; /* Tx Retry Success */
+ UINT32 TxAckRequired:1; /* Tx fail */
+ UINT32 wcid:8; /*wireless client index */
+ UINT32 SuccessRate:11; /*include MCS, mode ,shortGI, BW settingSame format as TXWI Word 0 Bit 31-16. */
+ UINT32 eTxBF:1; /* eTxBF enable */
+ UINT32 Sounding:1; /* Sounding enable */
+ UINT32 iTxBF:1; /* iTxBF enable */
+ UINT32 Reserve:2;
+ } field;
+ UINT32 word;
+} TX_STA_FIFO_STRUC, *PTX_STA_FIFO_STRUC;
+#endif
+
+#ifdef FIFO_EXT_SUPPORT
+
+#define TX_STA_FIFO_EXT 0x1798 /* Only work after RT53xx */
+/*
+ TX_STA_FIFO_EXT_STRUC: TX retry cnt for specific frame
+*/
+#ifdef RT_BIG_ENDIAN
+typedef union GNU_PACKED _TX_STA_FIFO_EXT_STRUC {
+ struct {
+ UINT32 Reserve:24;
+ UINT32 txRtyCnt:8; /* frame Tx retry cnt */
+ } field;
+ UINT32 word;
+} TX_STA_FIFO_EXT_STRUC, *PTX_STA_FIFO_EXT_STRUC;
+#else
+typedef union GNU_PACKED _TX_STA_FIFO_EXT_STRUC {
+ struct {
+ UINT32 txRtyCnt:8; /* frame Tx retry cnt */
+ UINT32 Reserve:24;
+ } field;
+ UINT32 word;
+} TX_STA_FIFO_EXT_STRUC, *PTX_STA_FIFO_EXT_STRUC;
+#endif
+
+#define WCID_TX_CNT_0 0x176c
+#define WCID_TX_CNT_1 0x1770
+#define WCID_TX_CNT_2 0x1774
+#define WCID_TX_CNT_3 0x1778
+#define WCID_TX_CNT_4 0x177c
+#define WCID_TX_CNT_5 0x1780
+#define WCID_TX_CNT_6 0x1784
+#define WCID_TX_CNT_7 0x1788
+#ifdef RT_BIG_ENDIAN
+typedef union GNU_PACKED _WCID_TX_CNT_STRUC {
+ struct {
+ UINT32 reTryCnt:16;
+ UINT32 succCnt:16;
+ } field;
+ UINT32 word;
+} WCID_TX_CNT_STRUC, *PWCID_TX_CNT_STRUC;
+#else
+typedef union GNU_PACKED _WCID_TX_CNT_STRUC {
+ struct {
+ UINT32 succCnt:16;
+ UINT32 reTryCnt:16;
+ } field;
+ UINT32 word;
+} WCID_TX_CNT_STRUC, *PWCID_TX_CNT_STRUC;
+#endif
+
+
+#define WCID_MAPPING_0 0x178c
+#define WCID_MAPPING_1 0x1790
+#ifdef RT_BIG_ENDIAN
+typedef union GNU_PACKED _WCID_MAPPING_STRUC {
+ struct {
+ UINT32 wcid3:8;
+ UINT32 wcid2:8;
+ UINT32 wcid1:8;
+ UINT32 wcid0:8;
+ } field;
+ UINT32 word;
+} WCID_MAPPING_STRUC, *PWCID_MAPPING_STRUC;
+#else
+typedef union GNU_PACKED _WCID_MAPPING_STRUC {
+ struct {
+ UINT32 wcid0:8;
+ UINT32 wcid1:8;
+ UINT32 wcid2:8;
+ UINT32 wcid3:8;
+ } field;
+ UINT32 word;
+} WCID_MAPPINGT_STRUC, *PWCID_MAPPING_STRUC;
+#endif
+#endif /* FIFO_EXT_SUPPORT */
+
+/* Debug counter */
+#define TX_AGG_CNT 0x171c
+#ifdef RT_BIG_ENDIAN
+typedef union _TX_AGG_CNT_STRUC {
+ struct {
+ USHORT AggTxCount;
+ USHORT NonAggTxCount;
+ } field;
+ UINT32 word;
+} TX_AGG_CNT_STRUC, *PTX_AGG_CNT_STRUC;
+#else
+typedef union _TX_AGG_CNT_STRUC {
+ struct {
+ USHORT NonAggTxCount;
+ USHORT AggTxCount;
+ } field;
+ UINT32 word;
+} TX_AGG_CNT_STRUC, *PTX_AGG_CNT_STRUC;
+#endif
+/* Debug counter */
+#define TX_AGG_CNT0 0x1720
+#ifdef RT_BIG_ENDIAN
+typedef union _TX_AGG_CNT0_STRUC {
+ struct {
+ USHORT AggSize2Count;
+ USHORT AggSize1Count;
+ } field;
+ UINT32 word;
+} TX_AGG_CNT0_STRUC, *PTX_AGG_CNT0_STRUC;
+#else
+typedef union _TX_AGG_CNT0_STRUC {
+ struct {
+ USHORT AggSize1Count;
+ USHORT AggSize2Count;
+ } field;
+ UINT32 word;
+} TX_AGG_CNT0_STRUC, *PTX_AGG_CNT0_STRUC;
+#endif
+/* Debug counter */
+#define TX_AGG_CNT1 0x1724
+#ifdef RT_BIG_ENDIAN
+typedef union _TX_AGG_CNT1_STRUC {
+ struct {
+ USHORT AggSize4Count;
+ USHORT AggSize3Count;
+ } field;
+ UINT32 word;
+} TX_AGG_CNT1_STRUC, *PTX_AGG_CNT1_STRUC;
+#else
+typedef union _TX_AGG_CNT1_STRUC {
+ struct {
+ USHORT AggSize3Count;
+ USHORT AggSize4Count;
+ } field;
+ UINT32 word;
+} TX_AGG_CNT1_STRUC, *PTX_AGG_CNT1_STRUC;
+#endif
+#define TX_AGG_CNT2 0x1728
+#ifdef RT_BIG_ENDIAN
+typedef union _TX_AGG_CNT2_STRUC {
+ struct {
+ USHORT AggSize6Count;
+ USHORT AggSize5Count;
+ } field;
+ UINT32 word;
+} TX_AGG_CNT2_STRUC, *PTX_AGG_CNT2_STRUC;
+#else
+typedef union _TX_AGG_CNT2_STRUC {
+ struct {
+ USHORT AggSize5Count;
+ USHORT AggSize6Count;
+ } field;
+ UINT32 word;
+} TX_AGG_CNT2_STRUC, *PTX_AGG_CNT2_STRUC;
+#endif
+/* Debug counter */
+#define TX_AGG_CNT3 0x172c
+#ifdef RT_BIG_ENDIAN
+typedef union _TX_AGG_CNT3_STRUC {
+ struct {
+ USHORT AggSize8Count;
+ USHORT AggSize7Count;
+ } field;
+ UINT32 word;
+} TX_AGG_CNT3_STRUC, *PTX_AGG_CNT3_STRUC;
+#else
+typedef union _TX_AGG_CNT3_STRUC {
+ struct {
+ USHORT AggSize7Count;
+ USHORT AggSize8Count;
+ } field;
+ UINT32 word;
+} TX_AGG_CNT3_STRUC, *PTX_AGG_CNT3_STRUC;
+#endif
+/* Debug counter */
+#define TX_AGG_CNT4 0x1730
+#ifdef RT_BIG_ENDIAN
+typedef union _TX_AGG_CNT4_STRUC {
+ struct {
+ USHORT AggSize10Count;
+ USHORT AggSize9Count;
+ } field;
+ UINT32 word;
+} TX_AGG_CNT4_STRUC, *PTX_AGG_CNT4_STRUC;
+#else
+typedef union _TX_AGG_CNT4_STRUC {
+ struct {
+ USHORT AggSize9Count;
+ USHORT AggSize10Count;
+ } field;
+ UINT32 word;
+} TX_AGG_CNT4_STRUC, *PTX_AGG_CNT4_STRUC;
+#endif
+#define TX_AGG_CNT5 0x1734
+#ifdef RT_BIG_ENDIAN
+typedef union _TX_AGG_CNT5_STRUC {
+ struct {
+ USHORT AggSize12Count;
+ USHORT AggSize11Count;
+ } field;
+ UINT32 word;
+} TX_AGG_CNT5_STRUC, *PTX_AGG_CNT5_STRUC;
+#else
+typedef union _TX_AGG_CNT5_STRUC {
+ struct {
+ USHORT AggSize11Count;
+ USHORT AggSize12Count;
+ } field;
+ UINT32 word;
+} TX_AGG_CNT5_STRUC, *PTX_AGG_CNT5_STRUC;
+#endif
+#define TX_AGG_CNT6 0x1738
+#ifdef RT_BIG_ENDIAN
+typedef union _TX_AGG_CNT6_STRUC {
+ struct {
+ USHORT AggSize14Count;
+ USHORT AggSize13Count;
+ } field;
+ UINT32 word;
+} TX_AGG_CNT6_STRUC, *PTX_AGG_CNT6_STRUC;
+#else
+typedef union _TX_AGG_CNT6_STRUC {
+ struct {
+ USHORT AggSize13Count;
+ USHORT AggSize14Count;
+ } field;
+ UINT32 word;
+} TX_AGG_CNT6_STRUC, *PTX_AGG_CNT6_STRUC;
+#endif
+#define TX_AGG_CNT7 0x173c
+#ifdef RT_BIG_ENDIAN
+typedef union _TX_AGG_CNT7_STRUC {
+ struct {
+ USHORT AggSize16Count;
+ USHORT AggSize15Count;
+ } field;
+ UINT32 word;
+} TX_AGG_CNT7_STRUC, *PTX_AGG_CNT7_STRUC;
+#else
+typedef union _TX_AGG_CNT7_STRUC {
+ struct {
+ USHORT AggSize15Count;
+ USHORT AggSize16Count;
+ } field;
+ UINT32 word;
+} TX_AGG_CNT7_STRUC, *PTX_AGG_CNT7_STRUC;
+#endif
+
+typedef union _TX_AGG_CNTN_STRUC {
+ struct {
+#ifdef RT_BIG_ENDIAN
+ USHORT AggSizeHighCount;
+ USHORT AggSizeLowCount;
+#else
+ USHORT AggSizeLowCount;
+ USHORT AggSizeHighCount;
+#endif
+ } field;
+ UINT32 word;
+} TX_AGG_CNTN_STRUC, *PTX_AGG_CNTN_STRUC;
+
+
+#define MPDU_DENSITY_CNT 0x1740
+#ifdef RT_BIG_ENDIAN
+typedef union _MPDU_DEN_CNT_STRUC {
+ struct {
+ USHORT RXZeroDelCount; /*RX zero length delimiter count */
+ USHORT TXZeroDelCount; /*TX zero length delimiter count */
+ } field;
+ UINT32 word;
+} MPDU_DEN_CNT_STRUC, *PMPDU_DEN_CNT_STRUC;
+#else
+typedef union _MPDU_DEN_CNT_STRUC {
+ struct {
+ USHORT TXZeroDelCount; /*TX zero length delimiter count */
+ USHORT RXZeroDelCount; /*RX zero length delimiter count */
+ } field;
+ UINT32 word;
+} MPDU_DEN_CNT_STRUC, *PMPDU_DEN_CNT_STRUC;
+#endif
+/* */
+/* TXRX control registers - base address 0x3000 */
+/* */
+/* rt2860b UNKNOWN reg use R/O Reg Addr 0x77d0 first.. */
+#define TXRX_CSR1 0x77d0
+
+/* */
+/* Security key table memory, base address = 0x1000 */
+/* */
+#define MAC_WCID_BASE 0x1800 /*8-bytes(use only 6-bytes) * 256 entry = */
+#define HW_WCID_ENTRY_SIZE 8
+#define PAIRWISE_KEY_TABLE_BASE 0x4000 /* 32-byte * 256-entry = -byte */
+#define HW_KEY_ENTRY_SIZE 0x20
+#define PAIRWISE_IVEIV_TABLE_BASE 0x6000 /* 8-byte * 256-entry = -byte */
+#define MAC_IVEIV_TABLE_BASE 0x6000 /* 8-byte * 256-entry = -byte */
+#define HW_IVEIV_ENTRY_SIZE 8
+#define MAC_WCID_ATTRIBUTE_BASE 0x6800 /* 4-byte * 256-entry = -byte */
+#define HW_WCID_ATTRI_SIZE 4
+#define WCID_RESERVED 0x6bfc
+#define SHARED_KEY_TABLE_BASE 0x6c00 /* 32-byte * 16-entry = 512-byte */
+#define SHARED_KEY_MODE_BASE 0x7000 /* 32-byte * 16-entry = 512-byte */
+#define HW_SHARED_KEY_MODE_SIZE 4
+#define SHAREDKEYTABLE 0
+#define PAIRWISEKEYTABLE 1
+
+/* This resgiser is ONLY be supported for RT3883 or later.
+ It conflicted with BCN#0 offset of previous chipset. */
+#define WAPI_PN_TABLE_BASE 0x7800
+#define WAPI_PN_ENTRY_SIZE 8
+
+#ifdef RT_BIG_ENDIAN
+typedef union _SHAREDKEY_MODE_STRUC {
+ struct {
+ UINT32 Bss1Key3CipherAlg:4;
+ UINT32 Bss1Key2CipherAlg:4;
+ UINT32 Bss1Key1CipherAlg:4;
+ UINT32 Bss1Key0CipherAlg:4;
+ UINT32 Bss0Key3CipherAlg:4;
+ UINT32 Bss0Key2CipherAlg:4;
+ UINT32 Bss0Key1CipherAlg:4;
+ UINT32 Bss0Key0CipherAlg:4;
+ } field;
+ UINT32 word;
+} SHAREDKEY_MODE_STRUC, *PSHAREDKEY_MODE_STRUC;
+#else
+typedef union _SHAREDKEY_MODE_STRUC {
+ struct {
+ UINT32 Bss0Key0CipherAlg:4;
+ UINT32 Bss0Key1CipherAlg:4;
+ UINT32 Bss0Key2CipherAlg:4;
+ UINT32 Bss0Key3CipherAlg:4;
+ UINT32 Bss1Key0CipherAlg:4;
+ UINT32 Bss1Key1CipherAlg:4;
+ UINT32 Bss1Key2CipherAlg:4;
+ UINT32 Bss1Key3CipherAlg:4;
+ } field;
+ UINT32 word;
+} SHAREDKEY_MODE_STRUC, *PSHAREDKEY_MODE_STRUC;
+#endif
+/* 64-entry for pairwise key table */
+typedef struct _HW_WCID_ENTRY { /* 8-byte per entry */
+ UCHAR Address[6];
+ UCHAR Rsv[2];
+} HW_WCID_ENTRY, PHW_WCID_ENTRY;
+
+
+/* ================================================================================= */
+/* WCID format */
+/* ================================================================================= */
+/*7.1 WCID ENTRY format : 8bytes */
+typedef struct _WCID_ENTRY_STRUC {
+ UCHAR RXBABitmap7; /* bit0 for TID8, bit7 for TID 15 */
+ UCHAR RXBABitmap0; /* bit0 for TID0, bit7 for TID 7 */
+ UCHAR MAC[6]; /* 0 for shared key table. 1 for pairwise key table */
+} WCID_ENTRY_STRUC, *PWCID_ENTRY_STRUC;
+
+/*8.1.1 SECURITY KEY format : 8DW */
+/* 32-byte per entry, total 16-entry for shared key table, 64-entry for pairwise key table */
+typedef struct _HW_KEY_ENTRY { /* 32-byte per entry */
+ UCHAR Key[16];
+ UCHAR TxMic[8];
+ UCHAR RxMic[8];
+} HW_KEY_ENTRY, *PHW_KEY_ENTRY;
+
+/*8.1.2 IV/EIV format : 2DW */
+
+/* RX attribute entry format : 1DW */
+#ifdef RT_BIG_ENDIAN
+typedef union _WCID_ATTRIBUTE_STRUC {
+ struct {
+ UINT32 WAPIKeyIdx:8;
+ UINT32 WAPI_rsv:8;
+ UINT32 WAPI_MCBC:1;
+ UINT32 rsv:3;
+ UINT32 BSSIdxExt:1;
+ UINT32 PairKeyModeExt:1;
+ UINT32 RXWIUDF:3;
+ UINT32 BSSIdx:3; /*multipleBSS index for the WCID */
+ UINT32 PairKeyMode:3;
+ UINT32 KeyTab:1; /* 0 for shared key table. 1 for pairwise key table */
+ } field;
+ UINT32 word;
+} WCID_ATTRIBUTE_STRUC, *PWCID_ATTRIBUTE_STRUC;
+#else
+typedef union _WCID_ATTRIBUTE_STRUC {
+ struct {
+ UINT32 KeyTab:1; /* 0 for shared key table. 1 for pairwise key table */
+ UINT32 PairKeyMode:3;
+ UINT32 BSSIdx:3; /*multipleBSS index for the WCID */
+ UINT32 RXWIUDF:3;
+ UINT32 PairKeyModeExt:1;
+ UINT32 BSSIdxExt:1;
+ UINT32 rsv:3;
+ UINT32 WAPI_MCBC:1;
+ UINT32 WAPI_rsv:8;
+ UINT32 WAPIKeyIdx:8;
+ } field;
+ UINT32 word;
+} WCID_ATTRIBUTE_STRUC, *PWCID_ATTRIBUTE_STRUC;
+#endif
+
+
+/* ================================================================================= */
+/* HOST-MCU communication data structure */
+/* ================================================================================= */
+
+/* */
+/* H2M_MAILBOX_CSR: Host-to-MCU Mailbox */
+/* */
+#ifdef RT_BIG_ENDIAN
+typedef union _H2M_MAILBOX_STRUC {
+ struct {
+ UINT32 Owner:8;
+ UINT32 CmdToken:8; /* 0xff tells MCU not to report CmdDoneInt after excuting the command */
+ UINT32 HighByte:8;
+ UINT32 LowByte:8;
+ } field;
+ UINT32 word;
+} H2M_MAILBOX_STRUC, *PH2M_MAILBOX_STRUC;
+#else
+typedef union _H2M_MAILBOX_STRUC {
+ struct {
+ UINT32 LowByte:8;
+ UINT32 HighByte:8;
+ UINT32 CmdToken:8;
+ UINT32 Owner:8;
+ } field;
+ UINT32 word;
+} H2M_MAILBOX_STRUC, *PH2M_MAILBOX_STRUC;
+#endif
+
+/* */
+/* M2H_CMD_DONE_CSR: MCU-to-Host command complete indication */
+/* */
+#ifdef RT_BIG_ENDIAN
+typedef union _M2H_CMD_DONE_STRUC {
+ struct {
+ UINT32 CmdToken3;
+ UINT32 CmdToken2;
+ UINT32 CmdToken1;
+ UINT32 CmdToken0;
+ } field;
+ UINT32 word;
+} M2H_CMD_DONE_STRUC, *PM2H_CMD_DONE_STRUC;
+#else
+typedef union _M2H_CMD_DONE_STRUC {
+ struct {
+ UINT32 CmdToken0;
+ UINT32 CmdToken1;
+ UINT32 CmdToken2;
+ UINT32 CmdToken3;
+ } field;
+ UINT32 word;
+} M2H_CMD_DONE_STRUC, *PM2H_CMD_DONE_STRUC;
+#endif
+
+
+/*NAV_TIME_CFG :NAV */
+#ifdef RT_BIG_ENDIAN
+typedef union _NAV_TIME_CFG_STRUC {
+ struct {
+ USHORT rsv:6;
+ USHORT ZeroSifs:1; /* Applied zero SIFS timer after OFDM RX 0: disable */
+ USHORT Eifs:9; /* in unit of 1-us */
+ UCHAR SlotTime; /* in unit of 1-us */
+ UCHAR Sifs; /* in unit of 1-us */
+ } field;
+ UINT32 word;
+} NAV_TIME_CFG_STRUC, *PNAV_TIME_CFG_STRUC;
+#else
+typedef union _NAV_TIME_CFG_STRUC {
+ struct {
+ UCHAR Sifs; /* in unit of 1-us */
+ UCHAR SlotTime; /* in unit of 1-us */
+ USHORT Eifs:9; /* in unit of 1-us */
+ USHORT ZeroSifs:1; /* Applied zero SIFS timer after OFDM RX 0: disable */
+ USHORT rsv:6;
+ } field;
+ UINT32 word;
+} NAV_TIME_CFG_STRUC, *PNAV_TIME_CFG_STRUC;
+#endif
+
+
+/* */
+/* RX_FILTR_CFG: /RX configuration register */
+/* */
+#ifdef RT_BIG_ENDIAN
+typedef union RX_FILTR_CFG_STRUC {
+ struct {
+ UINT32 :15;
+ UINT32 DropRsvCntlType:1;
+
+ UINT32 DropBAR:1; /* */
+ UINT32 DropBA:1; /* */
+ UINT32 DropPsPoll:1; /* Drop Ps-Poll */
+ UINT32 DropRts:1; /* Drop Ps-Poll */
+
+ UINT32 DropCts:1; /* Drop Ps-Poll */
+ UINT32 DropAck:1; /* Drop Ps-Poll */
+ UINT32 DropCFEnd:1; /* Drop Ps-Poll */
+ UINT32 DropCFEndAck:1; /* Drop Ps-Poll */
+
+ UINT32 DropDuplicate:1; /* Drop duplicate frame */
+ UINT32 DropBcast:1; /* Drop broadcast frames */
+ UINT32 DropMcast:1; /* Drop multicast frames */
+ UINT32 DropVerErr:1; /* Drop version error frame */
+
+ UINT32 DropNotMyBSSID:1; /* Drop fram ToDs bit is true */
+ UINT32 DropNotToMe:1; /* Drop not to me unicast frame */
+ UINT32 DropPhyErr:1; /* Drop physical error */
+ UINT32 DropCRCErr:1; /* Drop CRC error */
+ } field;
+ UINT32 word;
+} RX_FILTR_CFG_STRUC, *PRX_FILTR_CFG_STRUC;
+#else
+typedef union _RX_FILTR_CFG_STRUC {
+ struct {
+ UINT32 DropCRCErr:1; /* Drop CRC error */
+ UINT32 DropPhyErr:1; /* Drop physical error */
+ UINT32 DropNotToMe:1; /* Drop not to me unicast frame */
+ UINT32 DropNotMyBSSID:1; /* Drop fram ToDs bit is true */
+
+ UINT32 DropVerErr:1; /* Drop version error frame */
+ UINT32 DropMcast:1; /* Drop multicast frames */
+ UINT32 DropBcast:1; /* Drop broadcast frames */
+ UINT32 DropDuplicate:1; /* Drop duplicate frame */
+
+ UINT32 DropCFEndAck:1; /* Drop Ps-Poll */
+ UINT32 DropCFEnd:1; /* Drop Ps-Poll */
+ UINT32 DropAck:1; /* Drop Ps-Poll */
+ UINT32 DropCts:1; /* Drop Ps-Poll */
+
+ UINT32 DropRts:1; /* Drop Ps-Poll */
+ UINT32 DropPsPoll:1; /* Drop Ps-Poll */
+ UINT32 DropBA:1; /* */
+ UINT32 DropBAR:1; /* */
+
+ UINT32 DropRsvCntlType:1;
+ UINT32 :15;
+ } field;
+ UINT32 word;
+} RX_FILTR_CFG_STRUC, *PRX_FILTR_CFG_STRUC;
+#endif
+
+
+
+
+/* */
+/* PHY_CSR4: RF serial control register */
+/* */
+#ifdef RT_BIG_ENDIAN
+typedef union _PHY_CSR4_STRUC {
+ struct {
+ UINT32 Busy:1; /* 1: ASIC is busy execute RF programming. */
+ UINT32 PLL_LD:1; /* RF PLL_LD status */
+ UINT32 IFSelect:1; /* 1: select IF to program, 0: select RF to program */
+ UINT32 NumberOfBits:5; /* Number of bits used in RFRegValue (I:20, RFMD:22) */
+ UINT32 RFRegValue:24; /* Register value (include register id) serial out to RF/IF chip. */
+ } field;
+ UINT32 word;
+} PHY_CSR4_STRUC, *PPHY_CSR4_STRUC;
+#else
+typedef union _PHY_CSR4_STRUC {
+ struct {
+ UINT32 RFRegValue:24; /* Register value (include register id) serial out to RF/IF chip. */
+ UINT32 NumberOfBits:5; /* Number of bits used in RFRegValue (I:20, RFMD:22) */
+ UINT32 IFSelect:1; /* 1: select IF to program, 0: select RF to program */
+ UINT32 PLL_LD:1; /* RF PLL_LD status */
+ UINT32 Busy:1; /* 1: ASIC is busy execute RF programming. */
+ } field;
+ UINT32 word;
+} PHY_CSR4_STRUC, *PPHY_CSR4_STRUC;
+#endif
+
+
+/* */
+/* SEC_CSR5: shared key table security mode register */
+/* */
+#ifdef RT_BIG_ENDIAN
+typedef union _SEC_CSR5_STRUC {
+ struct {
+ UINT32 :1;
+ UINT32 Bss3Key3CipherAlg:3;
+ UINT32 :1;
+ UINT32 Bss3Key2CipherAlg:3;
+ UINT32 :1;
+ UINT32 Bss3Key1CipherAlg:3;
+ UINT32 :1;
+ UINT32 Bss3Key0CipherAlg:3;
+ UINT32 :1;
+ UINT32 Bss2Key3CipherAlg:3;
+ UINT32 :1;
+ UINT32 Bss2Key2CipherAlg:3;
+ UINT32 :1;
+ UINT32 Bss2Key1CipherAlg:3;
+ UINT32 :1;
+ UINT32 Bss2Key0CipherAlg:3;
+ } field;
+ UINT32 word;
+} SEC_CSR5_STRUC, *PSEC_CSR5_STRUC;
+#else
+typedef union _SEC_CSR5_STRUC {
+ struct {
+ UINT32 Bss2Key0CipherAlg:3;
+ UINT32 :1;
+ UINT32 Bss2Key1CipherAlg:3;
+ UINT32 :1;
+ UINT32 Bss2Key2CipherAlg:3;
+ UINT32 :1;
+ UINT32 Bss2Key3CipherAlg:3;
+ UINT32 :1;
+ UINT32 Bss3Key0CipherAlg:3;
+ UINT32 :1;
+ UINT32 Bss3Key1CipherAlg:3;
+ UINT32 :1;
+ UINT32 Bss3Key2CipherAlg:3;
+ UINT32 :1;
+ UINT32 Bss3Key3CipherAlg:3;
+ UINT32 :1;
+ } field;
+ UINT32 word;
+} SEC_CSR5_STRUC, *PSEC_CSR5_STRUC;
+#endif
+
+
+/* */
+/* HOST_CMD_CSR: For HOST to interrupt embedded processor */
+/* */
+#ifdef RT_BIG_ENDIAN
+typedef union _HOST_CMD_CSR_STRUC {
+ struct {
+ UINT32 Rsv:24;
+ UINT32 HostCommand:8;
+ } field;
+ UINT32 word;
+} HOST_CMD_CSR_STRUC, *PHOST_CMD_CSR_STRUC;
+#else
+typedef union _HOST_CMD_CSR_STRUC {
+ struct {
+ UINT32 HostCommand:8;
+ UINT32 Rsv:24;
+ } field;
+ UINT32 word;
+} HOST_CMD_CSR_STRUC, *PHOST_CMD_CSR_STRUC;
+#endif
+
+
+/* */
+/* AIFSN_CSR: AIFSN for each EDCA AC */
+/* */
+
+
+
+/* */
+/* E2PROM_CSR: EEPROM control register */
+/* */
+#ifdef RT_BIG_ENDIAN
+typedef union _E2PROM_CSR_STRUC {
+ struct {
+ UINT32 Rsvd:25;
+ UINT32 LoadStatus:1; /* 1:loading, 0:done */
+ UINT32 Type:1; /* 1: 93C46, 0:93C66 */
+ UINT32 EepromDO:1;
+ UINT32 EepromDI:1;
+ UINT32 EepromCS:1;
+ UINT32 EepromSK:1;
+ UINT32 Reload:1; /* Reload EEPROM content, write one to reload, self-cleared. */
+ } field;
+ UINT32 word;
+} E2PROM_CSR_STRUC, *PE2PROM_CSR_STRUC;
+#else
+typedef union _E2PROM_CSR_STRUC {
+ struct {
+ UINT32 Reload:1; /* Reload EEPROM content, write one to reload, self-cleared. */
+ UINT32 EepromSK:1;
+ UINT32 EepromCS:1;
+ UINT32 EepromDI:1;
+ UINT32 EepromDO:1;
+ UINT32 Type:1; /* 1: 93C46, 0:93C66 */
+ UINT32 LoadStatus:1; /* 1:loading, 0:done */
+ UINT32 Rsvd:25;
+ } field;
+ UINT32 word;
+} E2PROM_CSR_STRUC, *PE2PROM_CSR_STRUC;
+#endif
+
+/* */
+/* QOS_CSR0: TXOP holder address0 register */
+/* */
+#ifdef RT_BIG_ENDIAN
+typedef union _QOS_CSR0_STRUC {
+ struct {
+ UCHAR Byte3; /* MAC address byte 3 */
+ UCHAR Byte2; /* MAC address byte 2 */
+ UCHAR Byte1; /* MAC address byte 1 */
+ UCHAR Byte0; /* MAC address byte 0 */
+ } field;
+ UINT32 word;
+} QOS_CSR0_STRUC, *PQOS_CSR0_STRUC;
+#else
+typedef union _QOS_CSR0_STRUC {
+ struct {
+ UCHAR Byte0; /* MAC address byte 0 */
+ UCHAR Byte1; /* MAC address byte 1 */
+ UCHAR Byte2; /* MAC address byte 2 */
+ UCHAR Byte3; /* MAC address byte 3 */
+ } field;
+ UINT32 word;
+} QOS_CSR0_STRUC, *PQOS_CSR0_STRUC;
+#endif
+
+/* */
+/* QOS_CSR1: TXOP holder address1 register */
+/* */
+#ifdef RT_BIG_ENDIAN
+typedef union _QOS_CSR1_STRUC {
+ struct {
+ UCHAR Rsvd1;
+ UCHAR Rsvd0;
+ UCHAR Byte5; /* MAC address byte 5 */
+ UCHAR Byte4; /* MAC address byte 4 */
+ } field;
+ UINT32 word;
+} QOS_CSR1_STRUC, *PQOS_CSR1_STRUC;
+#else
+typedef union _QOS_CSR1_STRUC {
+ struct {
+ UCHAR Byte4; /* MAC address byte 4 */
+ UCHAR Byte5; /* MAC address byte 5 */
+ UCHAR Rsvd0;
+ UCHAR Rsvd1;
+ } field;
+ UINT32 word;
+} QOS_CSR1_STRUC, *PQOS_CSR1_STRUC;
+#endif
+
+#define RF_CSR_CFG 0x500
+#ifdef RT_BIG_ENDIAN
+typedef union _RF_CSR_CFG_STRUC {
+ struct {
+ UINT Rsvd1:14; /* Reserved */
+ UINT RF_CSR_KICK:1; /* kick RF register read/write */
+ UINT RF_CSR_WR:1; /* 0: read 1: write */
+ UINT TESTCSR_RFACC_REGNUM:8; /* RF register ID */
+ UINT RF_CSR_DATA:8; /* DATA */
+ } field;
+ UINT word;
+} RF_CSR_CFG_STRUC, *PRF_CSR_CFG_STRUC;
+#else
+typedef union _RF_CSR_CFG_STRUC {
+ struct {
+ UINT RF_CSR_DATA:8; /* DATA */
+ UINT TESTCSR_RFACC_REGNUM:8; /* RF register ID */
+ UINT RF_CSR_WR:1; /* 0: read 1: write */
+ UINT RF_CSR_KICK:1; /* kick RF register read/write */
+ UINT Rsvd1:14; /* Reserved */
+ } field;
+ UINT word;
+} RF_CSR_CFG_STRUC, *PRF_CSR_CFG_STRUC;
+#endif
+
+#ifdef RT_BIG_ENDIAN
+typedef union _EEPROM_WORD_STRUC {
+ struct
+ {
+ UCHAR Byte1; // High Byte
+ UCHAR Byte0; // Low Byte
+ } field;
+ USHORT word;
+} EEPROM_WORD_STRUC, *PEEPROM_WORD_STRUC;
+#else
+typedef union _EEPROM_WORD_STRUC {
+ struct
+ {
+ UCHAR Byte0; // Low Byte
+ UCHAR Byte1; // High Byte
+ } field;
+ USHORT word;
+} EEPROM_WORD_STRUC, *PEEPROM_WORD_STRUC;
+#endif
+
+/* */
+/* Other on-chip shared memory space, base = 0x2000 */
+/* */
+
+/* CIS space - base address = 0x2000 */
+#define HW_CIS_BASE 0x2000
+
+/* Carrier-sense CTS frame base address. It's where mac stores carrier-sense frame for carrier-sense function. */
+#define HW_CS_CTS_BASE 0x7700
+/* DFS CTS frame base address. It's where mac stores CTS frame for DFS. */
+#define HW_DFS_CTS_BASE 0x7780
+#define HW_CTS_FRAME_SIZE 0x80
+
+/* 2004-11-08 john - since NULL frame won't be that long (256 byte). We steal 16 tail bytes */
+/* to save debugging settings */
+#define HW_DEBUG_SETTING_BASE 0x77f0 /* 0x77f0~0x77ff total 16 bytes */
+#define HW_DEBUG_SETTING_BASE2 0x7770 /* 0x77f0~0x77ff total 16 bytes */
+
+#ifdef WOW_SUPPORT
+/* WOW - NullFrame buffer */
+#define HW_NULL2_BASE 0x7780
+#define GPIO_HOLDTIME_OFFSET 0x7020 /* Target is 0x7023 */
+#endif /* WOW_SUPPORT */
+
+/*
+ On-chip BEACON frame space -
+ 1. HW_BEACON_OFFSET/64B must be 0;
+ 2. BCN_OFFSETx(0~) must also be changed in MACRegTable(common/rtmp_init.c)
+ */
+#define HW_BEACON_OFFSET 0x0200
+
+
+/* In order to support maximum 8 MBSS and its maximum length is 512 for each beacon
+ Three section discontinue memory segments will be used.
+ 1. The original region for BCN 0~3
+ 2. Extract memory from FCE table for BCN 4~5
+ 3. Extract memory from Pair-wise key table for BCN 6~7
+ It occupied those memory of wcid 238~253 for BCN 6
+ and wcid 222~237 for BCN 7 */
+/*#define HW_BEACON_MAX_COUNT 8 */
+#define HW_BEACON_MAX_SIZE(__pAd) ((__pAd)->chipCap.BcnMaxHwSize)
+#define HW_BEACON_BASE0(__pAd) ((__pAd)->chipCap.BcnBase[0])
+/*#define HW_BEACON_BASE1 0x7A00 */
+/*#define HW_BEACON_BASE2 0x7C00 */
+/*#define HW_BEACON_BASE3 0x7E00 */
+/*#define HW_BEACON_BASE4 0x7200 */
+/*#define HW_BEACON_BASE5 0x7400 */
+/*#define HW_BEACON_BASE6 0x5DC0 */
+/*#define HW_BEACON_BASE7 0x5BC0 */
+
+/* */
+/* Higher 8KB shared memory */
+/* */
+#define HW_BEACON_BASE0_REDIRECTION 0x4000
+#define HW_BEACON_BASE1_REDIRECTION 0x4200
+#define HW_BEACON_BASE2_REDIRECTION 0x4400
+#define HW_BEACON_BASE3_REDIRECTION 0x4600
+#define HW_BEACON_BASE4_REDIRECTION 0x4800
+#define HW_BEACON_BASE5_REDIRECTION 0x4A00
+#define HW_BEACON_BASE6_REDIRECTION 0x4C00
+#define HW_BEACON_BASE7_REDIRECTION 0x4E00
+
+
+/* HOST-MCU shared memory - base address = 0x2100 */
+#define HOST_CMD_CSR 0x404
+#define H2M_MAILBOX_CSR 0x7010
+#define H2M_MAILBOX_CID 0x7014
+#define H2M_MAILBOX_STATUS 0x701c
+#define H2M_INT_SRC 0x7024
+#define H2M_BBP_AGENT 0x7028
+#define M2H_CMD_DONE_CSR 0x000c
+#define MCU_TXOP_ARRAY_BASE 0x000c /* TODO: to be provided by Albert */
+#define MCU_TXOP_ENTRY_SIZE 32 /* TODO: to be provided by Albert */
+#define MAX_NUM_OF_TXOP_ENTRY 16 /* TODO: must be same with 8051 firmware */
+#define MCU_MBOX_VERSION 0x01 /* TODO: to be confirmed by Albert */
+#define MCU_MBOX_VERSION_OFFSET 5 /* TODO: to be provided by Albert */
+
+/* */
+/* Host DMA registers - base address 0x200 . TX0-3=EDCAQid0-3, TX4=HCCA, TX5=MGMT, */
+/* */
+/* */
+/* DMA RING DESCRIPTOR */
+/* */
+#define E2PROM_CSR 0x0004
+#define IO_CNTL_CSR 0x77d0
+
+
+
+/* ================================================================ */
+/* Tx / Rx / Mgmt ring descriptor definition */
+/* ================================================================ */
+
+/* the following PID values are used to mark outgoing frame type in TXD->PID so that */
+/* proper TX statistics can be collected based on these categories */
+/* b3-2 of PID field - */
+#define PID_MGMT 0x05
+#define PID_BEACON 0x0c
+#define PID_DATA_NORMALUCAST 0x02
+#define PID_DATA_AMPDU 0x04
+#define PID_DATA_NO_ACK 0x08
+#define PID_DATA_NOT_NORM_ACK 0x03
+/* value domain of pTxD->HostQId (4-bit: 0~15) */
+#define QID_AC_BK 1 /* meet ACI definition in 802.11e */
+#define QID_AC_BE 0 /* meet ACI definition in 802.11e */
+#define QID_AC_VI 2
+#define QID_AC_VO 3
+#define QID_HCCA 4
+#define NUM_OF_TX_RING 5
+#define QID_MGMT 13
+#define QID_RX 14
+#define QID_OTHER 15
+
+
+#ifdef SPECIFIC_BCN_BUF_SUPPORT
+#define LOWER_SHRMEM 0
+#define HIGHER_SHRMEM 1
+
+/* Shared memory access selection.
+ * 0: address 0x4000 ~ 0x7FFF mapping to lower 16kB of shared memory
+ * 1: address 0x4000 ~ 0x5FFF mapping to higher 8kB of shared memory
+ */
+#define RTMP_HIGH_SHARED_MEM_SET(_pAd) \
+ do{ \
+ if (_pAd->chipCap.FlgIsSupSpecBcnBuf == TRUE) \
+ { \
+ UINT32 regValue; \
+ \
+ if (_pAd->ShrMSel != HIGHER_SHRMEM) \
+ { \
+ _pAd->ShrMSel = HIGHER_SHRMEM; \
+ RTMP_IO_READ32(_pAd, PBF_SYS_CTRL, &regValue); \
+ RTMP_IO_WRITE32(_pAd, PBF_SYS_CTRL, regValue | (1 << 19)); \
+ } \
+ } \
+ } while(0)
+
+#define RTMP_LOW_SHARED_MEM_SET(_pAd) \
+ do{ \
+ if (_pAd->chipCap.FlgIsSupSpecBcnBuf == TRUE) \
+ { \
+ UINT32 regValue; \
+ \
+ if (_pAd->ShrMSel != LOWER_SHRMEM) \
+ { \
+ _pAd->ShrMSel = LOWER_SHRMEM; \
+ RTMP_IO_READ32(_pAd, PBF_SYS_CTRL, &regValue); \
+ RTMP_IO_WRITE32(_pAd, PBF_SYS_CTRL, regValue & ~(1 << 19)); \
+ } \
+ } \
+ } while(0)
+
+/*
+ When you swtich shr_mem to high, you can not access MCU, just like
+ H2M_MAILBOX_CSR 0x7010
+ H2M_MAILBOX_CID 0x7014
+ H2M_MAILBOX_STATUS 0x701c
+ H2M_INT_SRC 0x7024
+ H2M_BBP_AGENT 0x7028
+*/
+
+#ifdef RTMP_MAC_USB
+#define RTMP_MAC_SHR_MSEL_PROTECT_LOCK(__pAd, __IrqFlags) __IrqFlags = __IrqFlags;
+#define RTMP_MAC_SHR_MSEL_PROTECT_UNLOCK(__pAd, __IrqFlags) __IrqFlags = __IrqFlags;
+#endif /* RTMP_MAC_USB */
+
+#ifdef RTMP_MAC_USB
+ /*
+ Disable irq to make sure the shared memory status(Mac Reg : 0x0400, bit-19)
+ doesn't been changed.
+ Becasue the PRE-TBTT interrupt would change this status.
+ */
+#define RTMP_MAC_SHR_MSEL_LOCK(_pAd, _shr_msel, _irqFlag) \
+ do{ \
+ if (_pAd->chipCap.FlgIsSupSpecBcnBuf == TRUE) \
+ { \
+ UINT32 __regValue, __status = 0; \
+ \
+ RTMP_SEM_EVENT_WAIT(&_pAd->ShrMemSemaphore, __status); \
+ if (__status != 0) \
+ { \
+ DBGPRINT(RT_DEBUG_ERROR, ("SHR_MSEL: failed to get semaphore\n")); \
+ } \
+ \
+ _pAd->ShrMSel = _shr_msel; \
+ RTMP_IO_READ32(_pAd, PBF_SYS_CTRL, &__regValue); \
+ if (_shr_msel == HIGHER_SHRMEM) \
+ { \
+ RTMP_IO_WRITE32(_pAd, PBF_SYS_CTRL, __regValue | (1 << 19)); \
+ } \
+ else \
+ { \
+ RTMP_IO_WRITE32(_pAd, PBF_SYS_CTRL, __regValue & ~(1 << 19)); \
+ } \
+ } \
+ }while(0)
+
+
+#define RTMP_MAC_SHR_MSEL_UNLOCK(_pAd, _shr_msel, _irqFlag) \
+ do{ \
+ if (_pAd->chipCap.FlgIsSupSpecBcnBuf == TRUE) \
+ { \
+ UINT32 __regValue; \
+ \
+ _pAd->ShrMSel = _shr_msel; \
+ RTMP_IO_READ32(_pAd, PBF_SYS_CTRL, &__regValue); \
+ if (_shr_msel == HIGHER_SHRMEM) \
+ { \
+ RTMP_IO_WRITE32(_pAd, PBF_SYS_CTRL, __regValue | (1 << 19)); \
+ } \
+ else \
+ { \
+ RTMP_IO_WRITE32(_pAd, PBF_SYS_CTRL, __regValue & ~(1 << 19)); \
+ } \
+ RTMP_SEM_EVENT_UP(&_pAd->ShrMemSemaphore); \
+ } \
+ } while(0)
+#endif /* RTMP_MAC_USB */
+
+#else
+
+#define RTMP_MAC_SHR_MSEL_PROTECT_LOCK(__pAd, __IrqFlags) __IrqFlags = __IrqFlags;
+#define RTMP_MAC_SHR_MSEL_PROTECT_UNLOCK(__pAd, __IrqFlags) __IrqFlags = __IrqFlags;
+
+#endif /* SPECIFIC_BCN_BUF_SUPPORT */
+
+#ifdef RTMP_MAC_USB
+#ifdef DFS_SUPPORT
+#define BBPR127TABLE_OWNERID 0x4CA0
+#define BBPR127TABLE_OFFSET 0x4D00
+#endif /* DFS_SUPPORT */
+#endif /* RTMP_MAC_USB */
+
+#endif /* __RTMP_MAC_H__ */
+
diff --git a/cleopatre/devkit/rt5572drv/MODULE/include/chip/rtmp_phy.h b/cleopatre/devkit/rt5572drv/MODULE/include/chip/rtmp_phy.h
new file mode 100644
index 0000000000..5356cd4962
--- /dev/null
+++ b/cleopatre/devkit/rt5572drv/MODULE/include/chip/rtmp_phy.h
@@ -0,0 +1,646 @@
+/*
+ ***************************************************************************
+ * Ralink Tech Inc.
+ * 4F, No. 2 Technology 5th Rd.
+ * Science-based Industrial Park
+ * Hsin-chu, Taiwan, R.O.C.
+ *
+ * (c) Copyright 2002-2004, Ralink Technology, Inc.
+ *
+ * All rights reserved. Ralink's source code is an unpublished work and the
+ * use of a copyright notice does not imply otherwise. This source code
+ * contains confidential trade secret material of Ralink Tech. Any attemp
+ * or participation in deciphering, decoding, reverse engineering or in any
+ * way altering the source code is stricitly prohibited, unless the prior
+ * written consent of Ralink Technology, Inc. is obtained.
+ ***************************************************************************
+
+ Module Name:
+ rtmp_phy.h
+
+ Abstract:
+ Ralink Wireless Chip PHY(BBP/RF) related definition & structures
+
+ Revision History:
+ Who When What
+ -------- ---------- ----------------------------------------------
+*/
+
+#ifndef __RTMP_PHY_H__
+#define __RTMP_PHY_H__
+
+
+/*
+ RF sections
+*/
+#define RF_R00 0
+#define RF_R01 1
+#define RF_R02 2
+#define RF_R03 3
+#define RF_R04 4
+#define RF_R05 5
+#define RF_R06 6
+#define RF_R07 7
+#define RF_R08 8
+#define RF_R09 9
+#define RF_R10 10
+#define RF_R11 11
+#define RF_R12 12
+#define RF_R13 13
+#define RF_R14 14
+#define RF_R15 15
+#define RF_R16 16
+#define RF_R17 17
+#define RF_R18 18
+#define RF_R19 19
+#define RF_R20 20
+#define RF_R21 21
+#define RF_R22 22
+#define RF_R23 23
+#define RF_R24 24
+#define RF_R25 25
+#define RF_R26 26
+#define RF_R27 27
+#define RF_R28 28
+#define RF_R29 29
+#define RF_R30 30
+#define RF_R31 31
+#define RF_R32 32
+#define RF_R33 33
+#define RF_R34 34
+#define RF_R35 35
+#define RF_R36 36
+#define RF_R37 37
+#define RF_R38 38
+#define RF_R39 39
+#define RF_R40 40
+#define RF_R41 41
+#define RF_R42 42
+#define RF_R43 43
+#define RF_R44 44
+#define RF_R45 45
+#define RF_R46 46
+#define RF_R47 47
+#define RF_R48 48
+#define RF_R49 49
+#define RF_R50 50
+#define RF_R51 51
+#define RF_R52 52
+#define RF_R53 53
+#define RF_R54 54
+#define RF_R55 55
+#define RF_R56 56
+#define RF_R57 57
+#define RF_R58 58
+#define RF_R59 59
+#define RF_R60 60
+#define RF_R61 61
+#define RF_R62 62
+#define RF_R63 63
+
+
+/* value domain of pAd->RfIcType */
+#define RFIC_2820 1 /* 2.4G 2T3R */
+#define RFIC_2850 2 /* 2.4G/5G 2T3R */
+#define RFIC_2720 3 /* 2.4G 1T2R */
+#define RFIC_2750 4 /* 2.4G/5G 1T2R */
+#define RFIC_3020 5 /* 2.4G 1T1R */
+#define RFIC_2020 6 /* 2.4G B/G */
+#define RFIC_3021 7 /* 2.4G 1T2R */
+#define RFIC_3022 8 /* 2.4G 2T2R */
+#define RFIC_3052 9 /* 2.4G/5G 2T2R */
+#define RFIC_2853 10 /* 2.4G.5G 3T3R */
+#define RFIC_3320 11 /* 2.4G 1T1R with PA (RT3350/RT3370/RT3390) */
+#define RFIC_3322 12 /* 2.4G 2T2R with PA (RT3352/RT3371/RT3372/RT3391/RT3392) */
+#define RFIC_3053 13 /* 2.4G/5G 3T3R (RT3883/RT3563/RT3573/RT3593/RT3662) */
+#define RFIC_3853 13 /* 2.4G/5G 3T3R (RT3883/RT3563/RT3573/RT3593/RT3662) */
+#define RFIC_5592 14 /* 2.4G/5G */
+#define RFIC_UNKNOWN 0xff
+
+#define RFIC_IS_5G_BAND(__pAd) \
+ ((__pAd->RfIcType == RFIC_2850) || \
+ (__pAd->RfIcType == RFIC_2750) || \
+ (__pAd->RfIcType == RFIC_3052) || \
+ (__pAd->RfIcType == RFIC_2853) || \
+ (__pAd->RfIcType == RFIC_3053) || \
+ (__pAd->RfIcType == RFIC_3853) || \
+ (__pAd->RfIcType == RFIC_5592) || \
+ (__pAd->RfIcType == RFIC_UNKNOWN))
+
+/*
+ BBP sections
+*/
+#define BBP_R0 0 /* version */
+#define BBP_R1 1 /* TSSI */
+#define BBP_R2 2 /* TX configure */
+#define BBP_R3 3
+#define BBP_R4 4
+#define BBP_R5 5
+#define BBP_R6 6
+#define BBP_R10 10 /* Rate report */
+#define BBP_R14 14 /* RX configure */
+#define BBP_R16 16
+#define BBP_R17 17 /* RX sensibility */
+#define BBP_R18 18
+#define BBP_R20 20
+#define BBP_R21 21
+#define BBP_R22 22
+#define BBP_R23 23
+#define BBP_R24 24
+#define BBP_R25 25
+#define BBP_R26 26
+#define BBP_R27 27
+#define BBP_R31 31
+#define BBP_R47 47
+#define BBP_R49 49 /*TSSI */
+#define BBP_R50 50
+#define BBP_R51 51
+#define BBP_R52 52
+#define BBP_R53 53
+#define BBP_R54 54
+#define BBP_R55 55
+#define BBP_R60 60
+#define BBP_R57 57
+#define BBP_R62 62 /* Rx SQ0 Threshold HIGH */
+#define BBP_R63 63
+#define BBP_R64 64
+#define BBP_R65 65
+#define BBP_R66 66
+#define BBP_R67 67
+#define BBP_R68 68
+#define BBP_R69 69
+#define BBP_R70 70 /* Rx AGC SQ CCK Xcorr threshold */
+#define BBP_R73 73
+#define BBP_R74 74
+#define BBP_R75 75
+#define BBP_R76 76
+#define BBP_R77 77
+#define BBP_R78 78
+#define BBP_R79 79
+#define BBP_R80 80
+#define BBP_R81 81
+#define BBP_R82 82
+#define BBP_R83 83
+#define BBP_R84 84
+#define BBP_R86 86
+#define BBP_R88 88
+#define BBP_R91 91
+#define BBP_R92 92
+#define BBP_R94 94 /* Tx Gain Control */
+#define BBP_R95 95
+#define BBP_R98 98
+#define BBP_R103 103
+#define BBP_R104 104
+#define BBP_R105 105
+#define BBP_R106 106
+#define BBP_R107 107
+#define BBP_R108 108
+#define BBP_R109 109
+#define BBP_R110 110
+#define BBP_R113 113
+#define BBP_R114 114
+#define BBP_R115 115
+#define BBP_R116 116
+#define BBP_R117 117
+#define BBP_R118 118
+#define BBP_R119 119
+#define BBP_R120 120
+#define BBP_R121 121
+#define BBP_R122 122
+#define BBP_R123 123
+#define BBP_R126 126
+#define BBP_R127 127
+#define BBP_R128 128
+#define BBP_R129 129
+#define BBP_R130 130
+#define BBP_R131 131
+#define BBP_R133 133
+#define BBP_R134 134
+#define BBP_R135 135
+#define BBP_R137 137
+#define BBP_R138 138 /* add by johnli, RF power sequence setup, ADC dynamic on/off control */
+#define BBP_R140 140
+#define BBP_R141 141
+#define BBP_R142 142
+#define BBP_R143 143
+#define BBP_R148 148
+#define BBP_R150 150
+#define BBP_R151 151
+#define BBP_R152 152
+#define BBP_R153 153
+#define BBP_R154 154
+#define BBP_R155 155
+#define BBP_R158 158 /* Calibration register are accessed through R158 and R159 */
+#define BBP_R159 159
+#define BBP_R160 160 /* Tx BF control */
+#define BBP_R161 161
+#define BBP_R162 162
+#define BBP_R163 163
+#define BBP_R164 164
+
+#define BBP_R170 170
+#define BBP_R171 171
+#define BBP_R173 173
+#define BBP_R174 174
+#define BBP_R175 175
+#define BBP_R176 176
+#define BBP_R177 177
+#define BBP_R179 179
+#define BBP_R180 180
+#define BBP_R181 181
+#define BBP_R182 182
+#define BBP_R184 184
+#define BBP_R185 185
+#define BBP_R186 186
+#define BBP_R187 187
+#define BBP_R188 188
+#define BBP_R189 189
+#define BBP_R190 190
+#define BBP_R191 191
+#define BBP_R195 195
+#define BBP_R196 196
+#define BBP_R250 250
+#define BBP_R253 253
+#define BBP_R254 254
+#define BBP_R255 255
+
+#define BBPR94_DEFAULT 0x06 /* Add 1 value will gain 1db */
+
+typedef enum{
+ RX_CHAIN_0 = 1<<0,
+ RX_CHAIN_1 = 1<<1,
+ RX_CHAIN_2 = 1<<2,
+ RX_CHAIN_ALL = 0xf
+}RX_CHAIN_IDX;
+
+#ifdef RT_BIG_ENDIAN
+typedef union _BBP_R47_STRUC {
+ struct
+ {
+ UCHAR Adc6On:1;
+ UCHAR Reserved:2;
+ UCHAR TssiMode:2;
+ UCHAR TssiUpdateReq:1;
+ UCHAR TssiReportSel:2;
+ } field;
+
+ UCHAR byte;
+} BBP_R47_STRUC, *PBBP_R47_STRUC;
+#else
+typedef union _BBP_R47_STRUC {
+ struct
+ {
+ UCHAR TssiReportSel:2;
+ UCHAR TssiUpdateReq:1;
+ UCHAR TssiMode:2;
+ UCHAR Reserved:2;
+ UCHAR Adc6On:1;
+ } field;
+
+ UCHAR byte;
+} BBP_R47_STRUC, *PBBP_R47_STRUC;
+#endif
+
+/* */
+/* BBP R49 TSSI (Transmit Signal Strength Indicator) */
+/* */
+#ifdef RT_BIG_ENDIAN
+typedef union _BBP_R49_STRUC {
+ struct
+ {
+ UCHAR adc5_in_sel:1; /* 0: TSSI (from the external components, old version), 1: PSI (internal components, new version - RT3390) */
+ UCHAR bypassTSSIAverage:1; /* 0: the average TSSI (the average of the 16 samples), 1: the current TSSI */
+ UCHAR Reserved:1; /* Reserved field */
+ UCHAR TSSI:5; /* TSSI value */
+ } field;
+
+ UCHAR byte;
+} BBP_R49_STRUC, *PBBP_R49_STRUC;
+#else
+typedef union _BBP_R49_STRUC {
+ struct
+ {
+ UCHAR TSSI:5; /* TSSI value */
+ UCHAR Reserved:1; /* Reserved field */
+ UCHAR bypassTSSIAverage:1; /* 0: the average TSSI (the average of the 16 samples), 1: the current TSSI */
+ UCHAR adc5_in_sel:1; /* 0: TSSI (from the external components, old version), 1: PSI (internal components, new version - RT3390) */
+ } field;
+
+ UCHAR byte;
+} BBP_R49_STRUC, *PBBP_R49_STRUC;
+#endif
+
+/* */
+/* BBP R105 (FEQ control, MLD control and SIG remodulation) */
+/* */
+#ifdef RT_BIG_ENDIAN
+typedef union _BBP_R105_STRUC {
+ struct
+ {
+ UCHAR Reserve1:4; /* Reserved field */
+ UCHAR EnableSIGRemodulation:1; /* Enable the channel estimation updates based on remodulation of L-SIG and HT-SIG symbols. */
+ UCHAR MLDFor2Stream:1; /* Apply Maximum Likelihood Detection (MLD) for 2 stream case (reserved field if single RX) */
+ UCHAR IndependentFeedForwardCompensation:1; /* Apply independent feed-forward compensation for independent stream. */
+ UCHAR DetectSIGOnPrimaryChannelOnly:1; /* Under 40 MHz band, detect SIG on primary channel only. */
+ } field;
+
+ UCHAR byte;
+} BBP_R105_STRUC, *PBBP_R105_STRUC;
+#else
+typedef union _BBP_R105_STRUC {
+ struct
+ {
+ UCHAR DetectSIGOnPrimaryChannelOnly:1; /* Under 40 MHz band, detect SIG on primary channel only. */
+ UCHAR IndependentFeedForwardCompensation:1; /* Apply independent feed-forward compensation for independent stream. */
+ UCHAR MLDFor2Stream:1; /* Apply Maximum Likelihood Detection (MLD) for 2 stream case (reserved field if single RX) */
+ UCHAR EnableSIGRemodulation:1; /* Enable the channel estimation updates based on remodulation of L-SIG and HT-SIG symbols. */
+ UCHAR Reserve1:4; /* Reserved field */
+ } field;
+
+ UCHAR byte;
+} BBP_R105_STRUC, *PBBP_R105_STRUC;
+#endif
+
+/* */
+/* BBP R106 (GI remover) */
+/* */
+#ifdef RT_BIG_ENDIAN
+typedef union _BBP_R106_STRUC {
+ struct
+ {
+ UCHAR EnableLowPowerFSD:1; /* enable/disable the low power FSD */
+ UCHAR ShortGI_Offset40:4; /* Delay GI remover when the short GI is detected in 40MHz band (40M sampling rate) */
+ UCHAR ShortGI_Offset20:3; /* Delay GI remover when the short GI is detected in 20MHz band (20M sampling rate) */
+ } field;
+
+ UCHAR byte;
+} BBP_R106_STRUC, *PBBP_R106_STRUC;
+#else
+typedef union _BBP_R106_STRUC {
+ struct
+ {
+ UCHAR ShortGI_Offset20:3; /* Delay GI remover when the short GI is detected in 20MHz band (20M sampling rate) */
+ UCHAR ShortGI_Offset40:4; /* Delay GI remover when the short GI is detected in 40MHz band (40M sampling rate) */
+ UCHAR EnableLowPowerFSD:1; /* enable/disable the low power FSD */
+ } field;
+
+ UCHAR byte;
+} BBP_R106_STRUC, *PBBP_R106_STRUC;
+#endif
+
+/* */
+/* BBP R109 (Tx power control in 0.1dB step) */
+/* */
+#ifdef RT_BIG_ENDIAN
+typedef union _BBP_R109_STRUC {
+ struct
+ {
+ UCHAR Tx1PowerCtrl:4; /* Tx1 power control in 0.1dB step (valid: 0~10) */
+ UCHAR Tx0PowerCtrl:4; /* Tx0 power control in 0.1dB step (valid: 0~10) */
+ } field;
+
+ UCHAR byte;
+} BBP_R109_STRUC, *PBBP_R109_STRUC;
+#else
+typedef union _BBP_R109_STRUC {
+ struct
+ {
+ UCHAR Tx0PowerCtrl:4; /* Tx0 power control in 0.1dB step (valid: 0~10) */
+ UCHAR Tx1PowerCtrl:4; /* Tx0 power control in 0.1dB step (valid: 0~10) */
+ } field;
+
+ UCHAR byte;
+} BBP_R109_STRUC, *PBBP_R109_STRUC;
+#endif
+
+/* */
+/* BBP R110 (Tx power control in 0.1dB step) */
+/* */
+#ifdef RT_BIG_ENDIAN
+typedef union _BBP_R110_STRUC {
+ struct
+ {
+ UCHAR Tx2PowerCtrl:4; /* Tx2 power control in 0.1dB step (valid: 0~10) */
+ UCHAR AllTxPowerCtrl:4; /* All transmitters' fine power control in 0.1dB (valid: 0~10) */
+ } field;
+
+ UCHAR byte;
+} BBP_R110_STRUC, *PBBP_R110_STRUC;
+#else
+typedef union _BBP_R110_STRUC {
+ struct
+ {
+ UCHAR AllTxPowerCtrl:4; /* All transmitters' fine power control in 0.1dB (valid: 0~10) */
+ UCHAR Tx2PowerCtrl:4; /* Tx2 power control in 0.1dB step (valid: 0~10) */
+ } field;
+
+ UCHAR byte;
+} BBP_R110_STRUC, *PBBP_R110_STRUC;
+#endif
+
+/* */
+/* BBP R179 (Test config #1) */
+/* */
+#ifdef RT_BIG_ENDIAN
+typedef union _BBP_R179_STRUC {
+ struct
+ {
+ UCHAR DataIndex1:8; /* Data index #1 */
+ } field;
+
+ UCHAR byte;
+} BBP_R179_STRUC, *PBBP_R179_STRUC;
+#else
+typedef union _BBP_R179_STRUC {
+ struct
+ {
+ UCHAR DataIndex1:8; /* Data index #1 */
+ } field;
+
+ UCHAR byte;
+} BBP_R179_STRUC, *PBBP_R179_STRUC;
+#endif /* RT_BIG_ENDIAN */
+
+/* */
+/* BBP R180 (Test config #2) */
+/* */
+#ifdef RT_BIG_ENDIAN
+typedef union _BBP_R180_STRUC {
+ struct
+ {
+ UCHAR DataIndex2:8; /* Data index #2 */
+ } field;
+
+ UCHAR byte;
+} BBP_R180_STRUC, *PBBP_R180_STRUC;
+#else
+typedef union _BBP_R180_STRUC {
+ struct
+ {
+ UCHAR DataIndex2:8; /* Data index #2 */
+ } field;
+
+ UCHAR byte;
+} BBP_R180_STRUC, *PBBP_R180_STRUC;
+#endif /* RT_BIG_ENDIAN */
+
+/* */
+/* BBP R182 (Test data port) */
+/* */
+#ifdef RT_BIG_ENDIAN
+typedef union _BBP_R182_STRUC {
+ struct
+ {
+ UCHAR DataArray:8; /* Data array indexed by BBP R179 and R180 */
+ } field;
+
+ UCHAR byte;
+} BBP_R182_STRUC, *PBBP_R182_STRUC;
+#else
+typedef union _BBP_R182_STRUC {
+ struct
+ {
+ UCHAR DataArray:8; /* Data array indexed by BBP R179 and R180 */
+ } field;
+
+ UCHAR byte;
+} BBP_R182_STRUC, *PBBP_R182_STRUC;
+#endif /* RT_BIG_ENDIAN */
+
+#if defined(RT5370) || defined(RT5390) || defined(RT3290) //for hw antenna diversity (PPAD)
+ #define MAX_BBP_ID 255
+#elif defined(RT30xx)
+ /* edit by johnli, RF power sequence setup, add BBP R138 for ADC dynamic on/off control */
+#ifdef RT5592
+ #define MAX_BBP_ID 255
+#else
+ #define MAX_BBP_ID 185
+#endif
+#elif defined(RT2883)
+ #define MAX_BBP_ID 180
+#else
+ #define MAX_BBP_ID 136
+#endif /* RT30xx */
+
+ #define MAX_BBP_MSG_SIZE 4096
+
+
+#ifdef RT5572
+#undef MAX_BBP_ID
+#define MAX_BBP_ID 248
+#undef MAX_BBP_MSG_SIZE
+#define MAX_BBP_MSG_SIZE 4096
+#endif
+
+
+/* */
+/* BBP & RF are using indirect access. Before write any value into it. */
+/* We have to make sure there is no outstanding command pending via checking busy bit. */
+/* */
+#define MAX_BUSY_COUNT 100 /* Number of retry before failing access BBP & RF indirect register */
+
+/*#define PHY_TR_SWITCH_TIME 5 // usec */
+
+/*#define BBP_R17_LOW_SENSIBILITY 0x50 */
+/*#define BBP_R17_MID_SENSIBILITY 0x41 */
+/*#define BBP_R17_DYNAMIC_UP_BOUND 0x40 */
+
+#define RSSI_FOR_VERY_LOW_SENSIBILITY -35
+#define RSSI_FOR_LOW_SENSIBILITY -58
+#define RSSI_FOR_MID_LOW_SENSIBILITY -65 /*-80*/
+#define RSSI_FOR_MID_SENSIBILITY -90
+
+/*****************************************************************************
+ RF register Read/Write marco definition
+ *****************************************************************************/
+
+#ifdef RTMP_MAC_USB
+#define RTMP_RF_IO_WRITE32(_A, _V) RTUSBWriteRFRegister(_A, _V)
+#endif /* RTMP_MAC_USB */
+
+
+#ifdef RT30xx
+#define RTMP_RF_IO_READ8_BY_REG_ID(_A, _I, _pV) RT30xxReadRFRegister(_A, _I, _pV)
+#define RTMP_RF_IO_WRITE8_BY_REG_ID(_A, _I, _V) RT30xxWriteRFRegister(_A, _I, _V)
+#endif /* RT30xx */
+
+
+/*****************************************************************************
+ BBP register Read/Write marco definitions.
+ we read/write the bbp value by register's ID.
+ Generate PER to test BA
+ *****************************************************************************/
+
+#ifdef CARRIER_DETECTION_SUPPORT
+/*TONE_RADAR_DETECT_V2*/
+#define RTMP_CARRIER_IO_READ8(_A, _I, _V) \
+{ \
+ RTMP_BBP_IO_WRITE8_BY_REG_ID(_A, BBP_R184, _I); \
+ RTMP_BBP_IO_READ8_BY_REG_ID(_A, BBP_R185, _V); \
+}
+#define RTMP_CARRIER_IO_WRITE8(_A, _I, _V) \
+{ \
+ RTMP_BBP_IO_WRITE8_BY_REG_ID(_A, BBP_R184, _I); \
+ RTMP_BBP_IO_WRITE8_BY_REG_ID(_A, BBP_R185, _V); \
+}
+#endif /* CARRIER_DETECTION_SUPPORT */
+
+#ifdef DFS_SUPPORT
+#define RTMP_DFS_IO_READ8(_A, _I, _V) \
+{ \
+ RTMP_BBP_IO_WRITE8_BY_REG_ID(_A, BBP_R140, _I); \
+ RTMP_BBP_IO_READ8_BY_REG_ID(_A, BBP_R141, _V); \
+}
+
+#define RTMP_DFS_IO_WRITE8(_A, _I, _V) \
+{ \
+ RTMP_BBP_IO_WRITE8_BY_REG_ID(_A, BBP_R140, _I); \
+ RTMP_BBP_IO_WRITE8_BY_REG_ID(_A, BBP_R141, _V); \
+}
+#endif /*DFS_SUPPORT*/
+
+#ifdef RTMP_MAC_USB
+#define RTMP_BBP_IO_READ8_BY_REG_ID(_A, _I, _pV) RTUSBReadBBPRegister(_A, _I, _pV)
+#define RTMP_BBP_IO_WRITE8_BY_REG_ID(_A, _I, _V) RTUSBWriteBBPRegister(_A, _I, _V)
+#define BBP_IO_WRITE8_BY_REG_ID(_A, _I, _V) RTUSBWriteBBPRegister(_A, _I, _V)
+#define BBP_IO_READ8_BY_REG_ID(_A, _I, _pV) RTUSBReadBBPRegister(_A, _I, _pV)
+#endif /* RTMP_MAC_USB */
+
+
+#ifdef RT30xx
+
+#define RTMP_ASIC_MMPS_DISABLE(_pAd) \
+ do{ \
+ UCHAR _bbpData = 0; \
+ UINT32 _macData; \
+ /* disable MMPS BBP control register */ \
+ RTMP_BBP_IO_READ8_BY_REG_ID(_pAd, BBP_R3, &_bbpData); \
+ _bbpData &= ~(0x04); /*bit 2*/ \
+ RTMP_BBP_IO_WRITE8_BY_REG_ID(_pAd, BBP_R3, _bbpData); \
+ \
+ /* disable MMPS MAC control register */ \
+ RTMP_IO_READ32(_pAd, 0x1210, &_macData); \
+ _macData &= ~(0x09); /*bit 0, 3*/ \
+ RTMP_IO_WRITE32(_pAd, 0x1210, _macData); \
+ }while(0)
+
+
+#define RTMP_ASIC_MMPS_ENABLE(_pAd) \
+ do{ \
+ UCHAR _bbpData = 0; \
+ UINT32 _macData; \
+ /* enable MMPS BBP control register */ \
+ RTMP_BBP_IO_READ8_BY_REG_ID(_pAd, BBP_R3, &_bbpData); \
+ _bbpData |= (0x04); /*bit 2*/ \
+ RTMP_BBP_IO_WRITE8_BY_REG_ID(_pAd, BBP_R3, _bbpData); \
+ \
+ /* enable MMPS MAC control register */ \
+ RTMP_IO_READ32(_pAd, 0x1210, &_macData); \
+ _macData |= (0x09); /*bit 0, 3*/ \
+ RTMP_IO_WRITE32(_pAd, 0x1210, _macData); \
+ }while(0)
+
+#endif /* RT30xx */
+
+#endif /* __RTMP_PHY_H__ */
+