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authordufour2010-02-04 09:08:29 +0000
committerdufour2010-02-04 09:08:29 +0000
commit1c6368a9fc2835136bd7371f47caf452514c0433 (patch)
treeb59fe5de8e013319759ff606691a56421095497b /cesar
parentb4935c2d88932d7a04d2cfa22e7ea48605303e82 (diff)
cesar/ce/rx/bl: add a margin to apply to the BER target
Even if the TNS team does not said it should be FEC rate dependant, I think it will in the future. Also, there is no advanced test on the impact of this margin on the bit loading algorithm (no test vector delivered yet). git-svn-id: svn+ssh://pessac/svn/cesar/trunk@6685 017c9cb6-072f-447c-8318-d5b54f68fe89
Diffstat (limited to 'cesar')
-rw-r--r--cesar/ce/rx/bitloading/inc/ber.h13
-rw-r--r--cesar/ce/rx/bitloading/src/ber.c20
-rw-r--r--cesar/ce/rx/bitloading/src/bitloading.c10
-rw-r--r--cesar/ce/rx/bitloading/test/src/test_bl.c63
4 files changed, 106 insertions, 0 deletions
diff --git a/cesar/ce/rx/bitloading/inc/ber.h b/cesar/ce/rx/bitloading/inc/ber.h
index 6af58e409c..319ff73f5a 100644
--- a/cesar/ce/rx/bitloading/inc/ber.h
+++ b/cesar/ce/rx/bitloading/inc/ber.h
@@ -89,6 +89,11 @@ ce_rx_bl_ber_poly_coef[PHY_FEC_RATE_NB][CE_MOD_COUNT - 1];
*/
extern const u64 ce_rx_bl_initial_bpt[PHY_FEC_RATE_NB];
+/**
+ * Margin to apply to BER target before usage in bit loading algorithm.
+ */
+extern u64 ce_rx_bl_ber_margin_[PHY_FEC_RATE_NB];
+
BEGIN_DECLS
/**
@@ -137,6 +142,14 @@ ce_rx_bl_ber_vs_nsr (ce_rx_bl_ber_poly_coef_t *poly, u32 nsr, u64 ber_pt,
u64
ce_rx_bl_ber_pt_bpt (phy_fecrate_t fec_rate, u64 bpt);
+/**
+ * Change margin to apply to BER target before usage in the bit loading
+ * algorithms.
+ * \param margin_q margin to apply to BER target (depend on FEC rate)
+ */
+void
+ce_rx_bl_ber_margin_set (u64 margin_q[PHY_FEC_RATE_NB]);
+
END_DECLS
#endif /* ce_rx_bitloading_inc_ber_h */
diff --git a/cesar/ce/rx/bitloading/src/ber.c b/cesar/ce/rx/bitloading/src/ber.c
index c29e8e51e1..402774c1e2 100644
--- a/cesar/ce/rx/bitloading/src/ber.c
+++ b/cesar/ce/rx/bitloading/src/ber.c
@@ -18,6 +18,14 @@
#include "ce/rx/bitloading/inc/ber.h"
#include "ce/rx/bitloading/inc/poly.h"
+/**
+ * Default value of margin to apply to BER target.
+ * This value is apparently quantified on 53 bits.
+ *
+ * We want a value of 1.5% by default: 0.015 * 2^53.
+ */
+u64 ce_rx_bl_ber_margin_[] = { 135107988821115ull, 135107988821115ull };
+
/* Imported from
* http://stestephe/svn/spidcom_digital_svn/projects/DSP_350/DSP_chain/SW/Bit_Loading/BER_vs_NSR/Polynomes_BERinq_vs_NSRq_normalises.m
* Revision: 11128.
@@ -229,3 +237,15 @@ ce_rx_bl_ber_pt_bpt (phy_fecrate_t fec_rate, u64 bpt)
return ce_rx_bl_poly (ce_rx_bl_ber_consign_degrees[fec_rate],
ce_rx_bl_ber_consign_coefs[fec_rate], bpt);
}
+
+void
+ce_rx_bl_ber_margin_set (u64 margin_q[PHY_FEC_RATE_NB])
+{
+ /* Check parameter. */
+ dbg_assert (margin_q);
+
+ /* Store margin values. */
+ phy_fecrate_t i;
+ for (i = PHY_FEC_RATE_1_2; i < PHY_FEC_RATE_NB; i++)
+ ce_rx_bl_ber_margin_[i] = margin_q[i];
+}
diff --git a/cesar/ce/rx/bitloading/src/bitloading.c b/cesar/ce/rx/bitloading/src/bitloading.c
index 96ff2a2362..f47c63c3a2 100644
--- a/cesar/ce/rx/bitloading/src/bitloading.c
+++ b/cesar/ce/rx/bitloading/src/bitloading.c
@@ -227,6 +227,11 @@ ce_rx_bl_compute_tone_map_iterative (const u64 bpt_initial[PHY_FEC_RATE_NB],
tm[fec_rate] = tonemap_alloc ();
/* Get initial BER consign from initial bits per tone. */
ber_cur = ce_rx_bl_ber_pt_bpt (fec_rate, bpt_initial[fec_rate]);
+ /* Apply BER target margin. */
+ if (ber_cur > ce_rx_bl_ber_margin_[fec_rate])
+ ber_cur = ber_cur - ce_rx_bl_ber_margin_[fec_rate];
+ else
+ ber_cur = 0;
do
{
/* Optimize tone map to reach BER consign. */
@@ -238,6 +243,11 @@ ce_rx_bl_compute_tone_map_iterative (const u64 bpt_initial[PHY_FEC_RATE_NB],
ber_cur = ce_rx_bl_ber_pt_bpt
(fec_rate, (tm[fec_rate]->bits_per_symbol *
CE_RX_BL_BPT_QUANT_FACTOR) / tone_en);
+ /* Apply BER target margin. */
+ if (ber_cur > ce_rx_bl_ber_margin_[fec_rate])
+ ber_cur = ber_cur - ce_rx_bl_ber_margin_[fec_rate];
+ else
+ ber_cur = 0;
}
/* Repeat until no modification of the BER consign or until maximum
* number of iterations is reached. */
diff --git a/cesar/ce/rx/bitloading/test/src/test_bl.c b/cesar/ce/rx/bitloading/test/src/test_bl.c
index dd134f700e..533b715e39 100644
--- a/cesar/ce/rx/bitloading/test/src/test_bl.c
+++ b/cesar/ce/rx/bitloading/test/src/test_bl.c
@@ -667,6 +667,62 @@ test_suite_ce_rx_bl_nsr_margin (test_t t)
#undef NSR_MARGIN_VECTOR_COUNT
}
+/**
+ * Test suite to check BER target margin.
+ */
+static void
+test_suite_ce_rx_bl_ber_target_margin (test_t t)
+{
+ test_case_begin (t, "BER target margin");
+
+ ce_rx_bitloading_t bl;
+ ce_rx_bitloading_init (&bl);
+
+ /* BER target margin should be set to 1.5% -> 0.015 -> quantification
+ * is set to 2^53. */
+ const u64 ber_margin_default_value = 135107988821115ull;
+
+ test_begin (t, "BER target margin initialisation")
+ {
+ /* The BER target margin should be set to the same value for both FEC
+ * rate (in fact, it should not depend, but I guess it will in the
+ * future...). */
+ test_fail_if (ce_rx_bl_ber_margin_[PHY_FEC_RATE_1_2]
+ != ce_rx_bl_ber_margin_[PHY_FEC_RATE_16_21]);
+ test_fail_if (ce_rx_bl_ber_margin_[PHY_FEC_RATE_1_2]
+ != ber_margin_default_value);
+ } test_end;
+
+ test_begin (t, "BER target margin configuration")
+ {
+ u64 ber_margin[PHY_FEC_RATE_NB];
+ /* Disable BER target margin. */
+ ber_margin[PHY_FEC_RATE_1_2] = ber_margin[PHY_FEC_RATE_16_21] = 0ull;
+ ce_rx_bl_ber_margin_set (ber_margin);
+ test_fail_if (ce_rx_bl_ber_margin_[PHY_FEC_RATE_1_2] != 0ull);
+ test_fail_if (ce_rx_bl_ber_margin_[PHY_FEC_RATE_16_21] != 0ull);
+ /* Reset to default value only one. */
+ ber_margin[PHY_FEC_RATE_1_2] = ber_margin_default_value;
+ ber_margin[PHY_FEC_RATE_16_21] = 0ull;
+ ce_rx_bl_ber_margin_set (ber_margin);
+ test_fail_if (ce_rx_bl_ber_margin_[PHY_FEC_RATE_1_2]
+ != ber_margin_default_value);
+ test_fail_if (ce_rx_bl_ber_margin_[PHY_FEC_RATE_16_21]
+ != 0ull);
+ /* Reset to default value the other one. */
+ ber_margin[PHY_FEC_RATE_1_2] = ber_margin_default_value;
+ ber_margin[PHY_FEC_RATE_16_21] = ber_margin_default_value;
+ ce_rx_bl_ber_margin_set (ber_margin);
+ test_fail_if (ce_rx_bl_ber_margin_[PHY_FEC_RATE_1_2]
+ != ber_margin_default_value);
+ test_fail_if (ce_rx_bl_ber_margin_[PHY_FEC_RATE_16_21]
+ != ber_margin_default_value);
+ } test_end;
+
+ /* Clean. */
+ ce_rx_bitloading_uninit (&bl);
+}
+
int
main (int argc, char **argv)
{
@@ -678,6 +734,9 @@ main (int argc, char **argv)
/* NSR margin. */
test_suite_ce_rx_bl_nsr_margin (t);
+ /* BER target margin. */
+ test_suite_ce_rx_bl_ber_target_margin (t);
+
/* NSR must be rescaled (FIXME: this should be done in the vector itself,
* not in the code). */
uint i;
@@ -689,6 +748,10 @@ main (int argc, char **argv)
* CE_RX_BL_NSR_MARGIN_QUANT_FACTOR). */
ce_rx_bl_nsr_margin_set (CE_RX_BL_NSR_MARGIN_QUANT_FACTOR);
+ /* Disable BER target margin. */
+ u64 ber_margin_disable[PHY_FEC_RATE_NB] = { 0ull, 0ull };
+ ce_rx_bl_ber_margin_set (ber_margin_disable);
+
/* Start test suite for the CE RX bitloading FSM. */
test_suite_ce_rx_bl_fsm (t);