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authorJean-Philippe SAVE2012-09-05 08:51:39 +0200
committerCyril Jourdan2012-09-20 17:00:14 +0200
commitfb5a00f761290fff7892ec2740d3ce1b7b4d9022 (patch)
tree66caf26d40ffb1d21472683d40a749364b48e41f /cesar/hal/phy/src/phy.c
parent136c2c2ce6f38124876495e245e20f99753589a8 (diff)
cesar/hal/phy: invert afe reset polarity, closes #3249
Diffstat (limited to 'cesar/hal/phy/src/phy.c')
-rw-r--r--cesar/hal/phy/src/phy.c4
1 files changed, 4 insertions, 0 deletions
diff --git a/cesar/hal/phy/src/phy.c b/cesar/hal/phy/src/phy.c
index be8bd8eb45..e06a41b7ff 100644
--- a/cesar/hal/phy/src/phy.c
+++ b/cesar/hal/phy/src/phy.c
@@ -65,6 +65,9 @@
/** RegBank clock command AFE. */
#define PHY_RB_CLK_CMD_AFE (*(volatile u32 *) 0xC8040480)
+/** RegBank AFE reset polarity register. */
+#define PHY_RB_AFE_RST_POL (*(volatile u32 *) 0xC8040718)
+
/** RegBank reset register. */
#define PHY_RB_RST_GROUP (*(volatile u32 *) 0xC8040708)
@@ -493,6 +496,7 @@ static void
phy_init_dsp (void)
{
/* Activate clocks and release DSP reset. */
+ PHY_RB_AFE_RST_POL = 0;
PHY_RB_CLK_CMD_AFE = 1;
PHY_RB_CLK_CMD_DSP = 1;
PHY_RB_RST_GROUP &= ~BF_MASK (PHY_RB_RST_GROUP__DSP);