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authorschodet2008-06-19 14:47:28 +0000
committerschodet2008-06-19 14:47:28 +0000
commitbbb3dd3ac4c8af32e84af01a10602c412cedff68 (patch)
tree28eec058a222042c54fca34c64977f1674ca0aad /cesar/hal/phy/inc/regs.h
parent92c420f9b3be1f3570751e013613bf93caf87a61 (diff)
* hal/phy:
- update after hardware changes. git-svn-id: svn+ssh://pessac/svn/cesar/trunk@2387 017c9cb6-072f-447c-8318-d5b54f68fe89
Diffstat (limited to 'cesar/hal/phy/inc/regs.h')
-rw-r--r--cesar/hal/phy/inc/regs.h62
1 files changed, 28 insertions, 34 deletions
diff --git a/cesar/hal/phy/inc/regs.h b/cesar/hal/phy/inc/regs.h
index 4687411b31..0feef2403d 100644
--- a/cesar/hal/phy/inc/regs.h
+++ b/cesar/hal/phy/inc/regs.h
@@ -52,9 +52,11 @@ typedef u32 uint32_t;
#define PHY_PRATIC_CSMA__FALSE_ALARM 16, 16
#define PHY_PRATIC_CSMA__TX_PRIORITY_LOST 17, 17
#define PHY_PRATIC_CSMA__TX_WHILE_RX 18, 18
-#define PHY_PRATIC_CSMA__FALSE_ALARM_MASK 19, 19
-#define PHY_PRATIC_CSMA__TX_PRIORITY_LOST_MASK 20, 20
-#define PHY_PRATIC_CSMA__TX_WHILE_RX_MASK 21, 21
+#define PHY_PRATIC_CSMA__TX_CANCEL_DUE_TO_FALSE_ALARM 19, 19
+#define PHY_PRATIC_CSMA__FALSE_ALARM_MASK 20, 20
+#define PHY_PRATIC_CSMA__TX_PRIORITY_LOST_MASK 21, 21
+#define PHY_PRATIC_CSMA__TX_WHILE_RX_MASK 22, 22
+#define PHY_PRATIC_CSMA__TX_CANCEL_DUE_TO_FALSE_ALARM_MASK 23, 23
/* FFT_PARAM */
#define PHY_PRATIC_FFT_PARAM__SIZE 0, 0
@@ -79,10 +81,9 @@ typedef u32 uint32_t;
/*** DSP SS ***/
/* COMMON_MODE */
-#define PHY_DSPSS_COMMON_MODE__GLOBAL_MODE 1, 0
-#define PHY_DSPSS_COMMON_MODE__USE_CRC_FC 2, 2
-#define PHY_DSPSS_COMMON_MODE__USE_CRC_PB 3, 3
-#define PHY_DSPSS_COMMON_MODE__CLK_150MHZ 4, 4
+#define PHY_DSPSS_COMMON_MODE__USE_CRC_FC 0, 0
+#define PHY_DSPSS_COMMON_MODE__USE_CRC_PB 1, 1
+#define PHY_DSPSS_COMMON_MODE__CLK_150MHZ 2, 2
/* TMD_CTRL */
#define PHY_DSPSS_TMD_CTRL__BUSY 0, 0
@@ -101,6 +102,7 @@ typedef u32 uint32_t;
#define PHY_DSPSS_TX_PARAM__USE_ADAPT_TABLE 24, 24
#define PHY_DSPSS_TX_PARAM__USE_AMPLITUDE_MAP 25, 25
#define PHY_DSPSS_TX_PARAM__USE_SHAKER 26, 26
+#define PHY_DSPSS_TX_PARAM__SOUND_FRAME 27, 27
#define PHY_DSPSS_TX_PARAM__WRONG_CRC24 30, 30
#define PHY_DSPSS_TX_PARAM__MAMA_DEBUG_ENABLE 31, 31
# define PHY_DSPSS_TX_PARAM__DEFAULT \
@@ -108,13 +110,6 @@ typedef u32 uint32_t;
| BF_MASK (PHY_DSPSS_TX_PARAM__USE_SHAKER) \
)
-/* TX_GUARD_TABLE */
-#define PHY_DSPSS_TX_GUARD_TABLE__INDEX 7, 0
-#define PHY_DSPSS_TX_GUARD_TABLE__VALUE 19, 8
-# define PHY_DSPSS_TX_GUARD_TABLE__VALUE_417 417
-# define PHY_DSPSS_TX_GUARD_TABLE__VALUE_567 567
-# define PHY_DSPSS_TX_GUARD_TABLE__VALUE_3534 3534
-
/* TX_FC_10 */
#define PHY_DSPSS_TX_FC_10__FC 24, 0
#define PHY_DSPSS_TX_FC_10__CRC 31, 31
@@ -123,10 +118,13 @@ typedef u32 uint32_t;
#define PHY_DSPSS_RX_PARAM__PB_SIZE 0, 0
#define PHY_DSPSS_RX_PARAM__PB_RATE 1, 1
#define PHY_DSPSS_RX_PARAM__PB_MOD 3, 2
-#define PHY_DSPSS_RX_PARAM__LOG_SAMPLES 4, 4
-#define PHY_DSPSS_RX_PARAM__USE_COEFF 5, 5
+#define PHY_DSPSS_RX_PARAM__FC_MODE 5, 4
+#define PHY_DSPSS_TX_PARAM__SHORT_PPDU 6, 6
#define PHY_DSPSS_RX_PARAM__USE_SCRAMBLER 7, 7
#define PHY_DSPSS_RX_PARAM__TMBI 15, 8
+#define PHY_DSPSS_RX_PARAM__LOG_SAMPLES 16, 16
+#define PHY_DSPSS_RX_PARAM__USE_COEFF 17, 17
+#define PHY_DSPSS_RX_PARAM__SOUND_FRAME 27, 27
# define PHY_DSPSS_RX_PARAM__DEFAULT \
(BF_MASK (PHY_DSPSS_RX_PARAM__USE_SCRAMBLER) \
)
@@ -168,15 +166,14 @@ typedef u32 uint32_t;
/* HPAV_MASK */
#define PHY_DSPSS_HPAV_MASK__NB_CARRIER 10, 0
+#define PHY_DSPSS_HPAV_MASK__NB_CARRIER_10 18, 11
/* CHANNEL_ESTIM_COEF */
#define PHY_DSPSS_CHANNEL_ESTIM_COEF__COEF_PREAMBLE 4, 0
/* RESYS_PARAM */
-#define PHY_DSPSS_RESYS_PARAM__FC_MODE 1, 0
-#define PHY_DSPSS_RESYS_PARAM__SHORT_PPDU 2, 2
-#define PHY_DSPSS_RESYS_PARAM__RESYS_COND 3, 3
-#define PHY_DSPSS_RESYS_PARAM__RESYS_ON 4, 4
+#define PHY_DSPSS_RESYS_PARAM__RESYS_COND 0, 0
+#define PHY_DSPSS_RESYS_PARAM__RESYS_ON 1, 1
#define PHY_DSPSS_RESYS_PARAM__LAST_SYMB_INDEX 15, 7
/* RESYS_THRESHOLD */
@@ -205,26 +202,16 @@ typedef u32 uint32_t;
#define PHY_DSPSS_MAGIC_PARAM_2__CONSTANT_GAIN_THRESHOLD 31, 16
/* MAGIC_PARAM_3 */
-#define PHY_DSPSS_MAGIC_PARAM_3__MAX_GAIN 15, 0
+#define PHY_DSPSS_MAGIC_PARAM_3__MAX_GAIN 7, 0
+#define PHY_DSPSS_MAGIC_PARAM_3__MANUAL_PGA_VALUE 13, 8
+#define PHY_DSPSS_MAGIC_PARAM_3__PGA_MANUAL 15
#define PHY_DSPSS_MAGIC_PARAM_3__OVERFLOW_GAIN_RESET 23, 16
#define PHY_DSPSS_MAGIC_PARAM_3__AGC_MANUAL 24, 24
#define PHY_DSPSS_MAGIC_PARAM_3__AGC_MANUAL_START 25, 25
-#define PHY_DSPSS_MAGIC_PARAM_3__ACTIVATE_PWM 26, 26
-
-/* AFE_CONFIG */
-#define PHY_DSPSS_AFE_CONFIG__MANUAL_PGA_VALUE 5, 0
-#define PHY_DSPSS_AFE_CONFIG__PGA_MANUAL 7, 7
-#define PHY_DSPSS_AFE_CONFIG__PLC_RESET 8, 8
-#define PHY_DSPSS_AFE_CONFIG__PLC_MODE 9, 9
-#define PHY_DSPSS_AFE_CONFIG__PLC_CONFIG 10, 10
-#define PHY_DSPSS_AFE_CONFIG__PLC_POWER_DOWN 11, 11
-#define PHY_DSPSS_AFE_CONFIG__PLC_ATTENUATOR 12, 12
-#define PHY_DSPSS_AFE_CONFIG__PLC_RX_ENABLE 13, 13
-#define PHY_DSPSS_AFE_CONFIG__PLC_TX_ENABLE 14, 14
/* RESYS_DETECT_OFFSET */
#define PHY_DSPSS_RESYS_DETECT_OFFSET__PREAMBLE 11, 0
-#define PHY_DSPSS_RESYS_DETECT_OFFSET__MUFTI_START_ADDRESS 19, 16
+#define PHY_DSPSS_RESYS_DETECT_OFFSET__MUFTI_START_ADDRESS 29, 16
/* RESYS_DEBUG_1 */
#define PHY_DSPSS_RESYS_DEBUG_1__SYMBOL_COUNT 7, 0
@@ -240,6 +227,13 @@ typedef u32 uint32_t;
#define PHY_DSPSS_MABEILLE_MODE__DEBUG_MODE_PRE_MEM 3, 3
#define PHY_DSPSS_MABEILLE_MODE__DEBUG_MODE_PRS_MEM 4, 4
+/* TX_GUARD_LENGTH */
+# define PHY_DSPSS_TX_GUARD_LENGTH__VALUE_FC_10 192
+# define PHY_DSPSS_TX_GUARD_LENGTH__VALUE_FC_AV (1374 + 372)
+# define PHY_DSPSS_TX_GUARD_LENGTH__VALUE_417 (417 + 372)
+# define PHY_DSPSS_TX_GUARD_LENGTH__VALUE_567 (567 + 372)
+# define PHY_DSPSS_TX_GUARD_LENGTH__VALUE_3534 (3534 + 372)
+
/*** PB DMA ***/
/* CTRL_CONFIG */