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authorschodet2009-11-12 12:47:03 +0000
committerschodet2009-11-12 12:47:03 +0000
commit48b5b2c88d06621d7d69ab8a98a1376219024f0a (patch)
tree56b10d6cc7ed0ed5b5abc05d45f09bef2b2245f1 /cesar/ecos/packages/hal/sparc
parent6b0c3fcde0918855cc80c58b475f8de14bf8aa9c (diff)
cesar/ecos/packages/hal/sparc: add CPU usage trace, refs #685
This traces context switches, ISR and DSR. git-svn-id: svn+ssh://pessac/svn/cesar/trunk@6361 017c9cb6-072f-447c-8318-d5b54f68fe89
Diffstat (limited to 'cesar/ecos/packages/hal/sparc')
-rw-r--r--cesar/ecos/packages/hal/sparc/arch/current/include/hal_intr.h18
-rw-r--r--cesar/ecos/packages/hal/sparc/arch/current/src/context.S22
-rw-r--r--cesar/ecos/packages/hal/sparc/arch/current/src/vec_ivsr.S115
-rw-r--r--cesar/ecos/packages/hal/sparc/leon/current/cdl/hal_sparc_leon.cdl2
4 files changed, 156 insertions, 1 deletions
diff --git a/cesar/ecos/packages/hal/sparc/arch/current/include/hal_intr.h b/cesar/ecos/packages/hal/sparc/arch/current/include/hal_intr.h
index 53491b8811..a6f00a5eac 100644
--- a/cesar/ecos/packages/hal/sparc/arch/current/include/hal_intr.h
+++ b/cesar/ecos/packages/hal/sparc/arch/current/include/hal_intr.h
@@ -73,6 +73,24 @@
#define HAL_TRANSLATE_VECTOR(_vector_,_index_) _index_ = (_vector_)
//---------------------------------------------------------------------------
+// Trace DSR calls
+
+#include "hal/trace/trace_cpu.h"
+
+#if HAL_TRACE_CPU
+
+# ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK
+# error "not compatible with HAL_TRACE_CPU"
+# endif
+
+/* Hook on interrupt stack switch callback. */
+externC void hal_interrupt_stack_call_pending_DSRs(void);
+#define HAL_INTERRUPT_STACK_CALL_PENDING_DSRS() \
+ hal_interrupt_stack_call_pending_DSRs()
+
+#endif
+
+//---------------------------------------------------------------------------
// Routine to execute DSRs using separate interrupt stack
#ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK
diff --git a/cesar/ecos/packages/hal/sparc/arch/current/src/context.S b/cesar/ecos/packages/hal/sparc/arch/current/src/context.S
index 7ea8ab4afc..faf41b2c3d 100644
--- a/cesar/ecos/packages/hal/sparc/arch/current/src/context.S
+++ b/cesar/ecos/packages/hal/sparc/arch/current/src/context.S
@@ -58,6 +58,8 @@
#include <cyg/hal/arch.inc>
+#include "hal/trace/trace_cpu.h"
+
#define DELAYS_AFTER_WRPSR_SAME_WINDOW
#define DELAYS_AFTER_WRWIM
@@ -169,6 +171,26 @@ hal_thread_load_context:
!ld [ %l0 ], %g7 ! Get the next saved SP
ld [ %o0 ], %g7 ! Get the next saved SP
+
+#if HAL_TRACE_CPU
+ ! Trace.
+ ! load bare->data_tail and bare->data_end
+ sethi %hi(hal_trace_cpu_bare_buffer), %g1
+ ldd [ %g1 + %lo(hal_trace_cpu_bare_buffer) ], %g4
+ set HAL_TRACE_CPU_SWITCH_ID, %g2
+ sethi %hi(HAL_TRACE_CPU_DATE_ADDR), %g3
+ ld [ %g3 + %lo(HAL_TRACE_CPU_DATE_ADDR) ], %g3 ! load date
+ std %g2, [ %g4 ] ! store them
+ mov %sp, %g6 ! old SP, new SP is in %g7
+ std %g6, [ %g4 + 8 ] ! store them
+ add %g4, 16, %g4 ! increment bare->data_tail
+ cmp %g4, %g5 ! if same as bare->data_end
+ be,a 1f
+ ! set to bare->data, thanks to 16 byte alignment
+ ld [ %g1 + %lo(hal_trace_cpu_bare_buffer + 8) ], %g4
+ ! store modified bare->data_tail
+1: st %g4, [ %g1 + %lo(hal_trace_cpu_bare_buffer) ]
+#endif
! DISABLE INTERRUPTS *ONLY* NOT TRAPS
rd %psr, %g6
diff --git a/cesar/ecos/packages/hal/sparc/arch/current/src/vec_ivsr.S b/cesar/ecos/packages/hal/sparc/arch/current/src/vec_ivsr.S
index e220b09133..2914e4d4b1 100644
--- a/cesar/ecos/packages/hal/sparc/arch/current/src/vec_ivsr.S
+++ b/cesar/ecos/packages/hal/sparc/arch/current/src/vec_ivsr.S
@@ -75,6 +75,8 @@
#include <cyg/hal/hal_leon_regs.h>
#endif
+#include "hal/trace/trace_cpu.h"
+
!------------------------------------------------------------------------
#include <cyg/hal/vectors.h>
@@ -329,6 +331,28 @@ hal_default_interrupt_vsr:
not_gic2:
spurious_gic2:
#endif
+
+#if HAL_TRACE_CPU
+ ! Trace.
+ ! load bare->data_tail and bare->data_end
+ sethi %hi(hal_trace_cpu_bare_buffer), %o1
+ ldd [ %o1 + %lo(hal_trace_cpu_bare_buffer) ], %o2
+ set HAL_TRACE_CPU_ISR_ID, %o4
+ sethi %hi(HAL_TRACE_CPU_DATE_ADDR), %o5
+ ld [ %o5 + %lo(HAL_TRACE_CPU_DATE_ADDR) ], %o5 ! load date
+ std %o4, [ %o2 ] ! store them
+ mov %fp, %o4 ! interrupted SP
+ mov %l3, %o5 ! vector number
+ std %o4, [ %o2 + 8 ] ! store them
+ add %o2, 16, %o2 ! increment bare->data_tail
+ cmp %o2, %o3 ! if same as bare->data_end
+ be,a 1f
+ ! set to bare->data, thanks to 16 byte alignment
+ ld [ %o1 + %lo(hal_trace_cpu_bare_buffer + 8) ], %o2
+ ! store modified bare->data_tail
+1: st %o2, [ %o1 + %lo(hal_trace_cpu_bare_buffer) ]
+#endif
+
mov %l3, %o0
sll %l3, 2, %l3 ! %l3 to a word offset
sethi %hi(hal_interrupt_data), %l7
@@ -341,6 +365,27 @@ spurious_gic2:
call %l6
nop
+#if HAL_TRACE_CPU
+ ! Trace.
+ ! load bare->data_tail and bare->data_end
+ sethi %hi(hal_trace_cpu_bare_buffer), %o1
+ ldd [ %o1 + %lo(hal_trace_cpu_bare_buffer) ], %o2
+ set HAL_TRACE_CPU_ISR_EXIT_ID, %o4
+ sethi %hi(HAL_TRACE_CPU_DATE_ADDR), %o5
+ ld [ %o5 + %lo(HAL_TRACE_CPU_DATE_ADDR) ], %o5 ! load date
+ std %o4, [ %o2 ] ! store them
+ set 0, %o4 ! nothing
+ set 0, %o5 ! nothing
+ std %o4, [ %o2 + 8 ] ! store them
+ add %o2, 16, %o2 ! increment bare->data_tail
+ cmp %o2, %o3 ! if same as bare->data_end
+ be,a 1f
+ ! set to bare->data, thanks to 16 byte alignment
+ ld [ %o1 + %lo(hal_trace_cpu_bare_buffer + 8) ], %o2
+ ! store modified bare->data_tail
+1: st %o2, [ %o1 + %lo(hal_trace_cpu_bare_buffer) ]
+#endif
+
#ifdef CYGFUN_HAL_COMMON_KERNEL_SUPPORT
! We only need to call _interrupt_end() when there is a kernel
! present to do any tidying up.
@@ -626,4 +671,74 @@ hal_interrupt_stack_call_pending_DSRs:
!----------------------------------------------------------------------------
+#if HAL_TRACE_CPU
+
+ .global hal_interrupt_stack_call_pending_DSRs
+hal_interrupt_stack_call_pending_DSRs:
+#if !defined(CYGHWR_HAL_SPARC_FLAT)
+ save %sp, -24 * 4, %sp
+#else
+ add %sp, -26 * 4, %sp
+ st %i7, [ %sp + 24 * 4 ]
+ sub %sp, -26 * 4, %i7
+ st %o7, [ %sp + 25 * 4 ]
+#endif
+
+ ! Trace.
+ ! load bare->data_tail and bare->data_end
+ sethi %hi(hal_trace_cpu_bare_buffer), %o1
+ ldd [ %o1 + %lo(hal_trace_cpu_bare_buffer) ], %o2
+ set HAL_TRACE_CPU_DSR_ID, %o4
+ sethi %hi(HAL_TRACE_CPU_DATE_ADDR), %o5
+ ld [ %o5 + %lo(HAL_TRACE_CPU_DATE_ADDR) ], %o5 ! load date
+ std %o4, [ %o2 ] ! store them
+ mov %sp, %o4 ! SP
+ set 0, %o5 ! nothing
+ std %o4, [ %o2 + 8 ] ! store them
+ add %o2, 16, %o2 ! increment bare->data_tail
+ cmp %o2, %o3 ! if same as bare->data_end
+ be,a 1f
+ ! set to bare->data, thanks to 16 byte alignment
+ ld [ %o1 + %lo(hal_trace_cpu_bare_buffer + 8) ], %o2
+ ! store modified bare->data_tail
+1: st %o2, [ %o1 + %lo(hal_trace_cpu_bare_buffer) ]
+
+ .extern cyg_interrupt_call_pending_DSRs
+ call cyg_interrupt_call_pending_DSRs
+ nop
+
+ ! Trace.
+ ! load bare->data_tail and bare->data_end
+ sethi %hi(hal_trace_cpu_bare_buffer), %o1
+ ldd [ %o1 + %lo(hal_trace_cpu_bare_buffer) ], %o2
+ set HAL_TRACE_CPU_DSR_EXIT_ID, %o4
+ sethi %hi(HAL_TRACE_CPU_DATE_ADDR), %o5
+ ld [ %o5 + %lo(HAL_TRACE_CPU_DATE_ADDR) ], %o5 ! load date
+ std %o4, [ %o2 ] ! store them
+ set 0, %o4 ! nothing
+ set 0, %o5 ! nothing
+ std %o4, [ %o2 + 8 ] ! store them
+ add %o2, 16, %o2 ! increment bare->data_tail
+ cmp %o2, %o3 ! if same as bare->data_end
+ be,a 1f
+ ! set to bare->data, thanks to 16 byte alignment
+ ld [ %o1 + %lo(hal_trace_cpu_bare_buffer + 8) ], %o2
+ ! store modified bare->data_tail
+1: st %o2, [ %o1 + %lo(hal_trace_cpu_bare_buffer) ]
+
+#if !defined(CYGHWR_HAL_SPARC_FLAT)
+ ret
+ restore
+#else
+ sub %i7, 26 * 4, %sp
+ ld [ %sp + 24 * 4 ], %i7
+ ld [ %sp + 25 * 4 ], %o7
+ retl
+ add %sp, 26 * 4, %sp
+#endif
+
+#endif /* HAL_TRACE_CPU */
+
+!----------------------------------------------------------------------------
+
! end of vec_ivsr.S
diff --git a/cesar/ecos/packages/hal/sparc/leon/current/cdl/hal_sparc_leon.cdl b/cesar/ecos/packages/hal/sparc/leon/current/cdl/hal_sparc_leon.cdl
index fa2e7c2fb1..4026a2ea6f 100644
--- a/cesar/ecos/packages/hal/sparc/leon/current/cdl/hal_sparc_leon.cdl
+++ b/cesar/ecos/packages/hal/sparc/leon/current/cdl/hal_sparc_leon.cdl
@@ -143,7 +143,7 @@ cdl_package CYGPKG_HAL_SPARC_LEON {
display "Global compiler flags"
flavor data
no_define
- default_value { "-mcpu=v8 -mflat -Wall -Wpointer-arith -Wstrict-prototypes -Winline -Wundef -g -O2 -ffunction-sections -fdata-sections -fno-exceptions -fvtable-gc -finit-priority" }
+ default_value { "-mcpu=v8 -mflat -Wall -Wpointer-arith -Wstrict-prototypes -Winline -Wundef -g -O2 -ffunction-sections -fdata-sections -fno-exceptions -fvtable-gc -finit-priority -I\$(BASE) -I\$(OBJ_DIR)/inc" }
description "
This option controls the global compiler flags which
are used to compile all packages by