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authorBelkadi & Save2011-07-13 16:31:36 +0200
committerBelkadi & Save2011-07-13 17:44:42 +0200
commit3a0a84d043da191714d0e7ffc499d5f2f552f41a (patch)
tree0bb77e889bc0c545dc9fee50a636c2da77fad327
parenta3dab39f3157a8ff28b74e934d164aa4e3ebf3e2 (diff)
cleo/u-boot: fix LEON start instructions in SDRAM, closes #2599
A side effect of the fix "clock synchronisation for PRP bug"(commit 13c535e), is that the LEON reset is released during boot. Despite of being configured to halt (debug mode), it actually fetches and executes a few instructions from a preconfigured location in SDRAM. The problem is that this preconfigured location is not initialized, so the LEON is executing random code that may corrupt the boot process (for example, lock the AHB Bus). The present commit initializes the prefconfigured location with NOP instructions. In order to do that, the SDRAM needs to be initialized sooner in the boot process. So the order is now: - SDRAM init - Clock synchro for PRP bug - PLL init
-rw-r--r--cleopatre/u-boot-1.1.6/cpu/spc300/dsp.S22
-rw-r--r--cleopatre/u-boot-1.1.6/cpu/spc300/start.S29
2 files changed, 37 insertions, 14 deletions
diff --git a/cleopatre/u-boot-1.1.6/cpu/spc300/dsp.S b/cleopatre/u-boot-1.1.6/cpu/spc300/dsp.S
index 0ed489ea0d..1d0340cf0e 100644
--- a/cleopatre/u-boot-1.1.6/cpu/spc300/dsp.S
+++ b/cleopatre/u-boot-1.1.6/cpu/spc300/dsp.S
@@ -68,6 +68,28 @@
dsp_init:
ldr r0, =REGBANK_BASE
+/* Set PHY CPU start instructions */
+
+ /* Later, we will have to release the PHY CPU reset. PHY CPU will execute
+ * its start code in sdram, so we need to prepare it first. */
+
+ /* Change PHY processeur start address to SDRAM base addr */
+ setreg RB_LEON_ADD_START, 0x00000000
+
+ /* Set SDRAM with NOP instruction for PHY CPU */
+ ldr r2, =PHYS_SDRAM /* Physical address of PCPU for booting at 0 */
+ ldr r1, =0x01000000 /* NOP instruction for PCPU */
+ str r1, [r2], #4
+ str r1, [r2], #4
+ str r1, [r2], #4
+ str r1, [r2], #4
+ str r1, [r2], #4
+ str r1, [r2], #4
+ str r1, [r2], #4
+ str r1, [r2], #4
+
+/* End Set PHY CPU start instructions */
+
/* Assert DSP reset, Normally already done. */
setbit RB_RST_GROUP, RST_DSP
diff --git a/cleopatre/u-boot-1.1.6/cpu/spc300/start.S b/cleopatre/u-boot-1.1.6/cpu/spc300/start.S
index 9ca66207a9..42b2aa687a 100644
--- a/cleopatre/u-boot-1.1.6/cpu/spc300/start.S
+++ b/cleopatre/u-boot-1.1.6/cpu/spc300/start.S
@@ -355,13 +355,6 @@ poll_RB_CLK_DIV_STAT_ARM:
cmp r1, #CLK_DIV_ARM_2
bne poll_RB_CLK_DIV_STAT_ARM
- /*
- * Synchronise DSP
- */
- mov ip, lr
- bl dsp_init
- mov lr, ip
-
/*
* Detect NVRAM address
*/
@@ -369,13 +362,6 @@ poll_RB_CLK_DIV_STAT_ARM:
bl detect_nvram /* r10 will hold the NVRAM address */
mov lr, ip /* restore link */
- /*
- * Do PLL initialization (depending on nvram parameters Xclk and Freq)
- */
- mov ip, lr /* perserve link reg across call */
- bl pll_init /* we pass NVRAM addr in r10; do not corrupt r10 in this function */
- mov lr, ip /* restore link */
-
/*
* SDRAM and board specific bits setup prior to relocation.
*/
@@ -383,6 +369,21 @@ poll_RB_CLK_DIV_STAT_ARM:
bl sdram_init /* we pass NVRAM addr in r10; do not corrupt r10 in this function */
mov lr, ip /* restore link */
+
+ /*
+ * Synchronise DSP
+ */
+ mov ip, lr /* perserve link reg across call */
+ bl dsp_init /* we pass NVRAM addr in r10; do not corrupt r10 in this function */
+ mov lr, ip /* restore link */
+
+ /*
+ * Do PLL initialization (depending on nvram parameters Xclk and Freq)
+ */
+ mov ip, lr /* perserve link reg across call */
+ bl pll_init /* we pass NVRAM addr in r10; do not corrupt r10 in this function */
+ mov lr, ip /* restore link */
+
/*
* All vital periphs configured, exit cpu_init_crit
*/