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authorburg2006-03-12 19:46:18 +0000
committerburg2006-03-12 19:46:18 +0000
commit466ea4f42c922b0c45650cf6c5fa4fe67c8bb7df (patch)
tree8ddd71f6595978fd99e8cdc67bf4450c008ab5e8 /a
parent13b56b3d5689d797bcc325b261ea7d22889efb31 (diff)
Modification des schémas:
-correction des optocoupleurs -correction des branchements pour la partie turbine -correction des branchements autour du LMD18200 TODO_schema: -l'alimentation -choisir les composants -tout ça voila bref ... vous savez ...
Diffstat (limited to 'a')
-rw-r--r--a/puiss-barillet/note_programmeur.txt10
-rw-r--r--a/puiss-barillet/puiss-barillet.schbin90064 -> 122763 bytes
-rw-r--r--a/puiss-barillet/spec_turbine.txt5
3 files changed, 15 insertions, 0 deletions
diff --git a/a/puiss-barillet/note_programmeur.txt b/a/puiss-barillet/note_programmeur.txt
new file mode 100644
index 0000000..5d7a34f
--- /dev/null
+++ b/a/puiss-barillet/note_programmeur.txt
@@ -0,0 +1,10 @@
+SIGNAL TRANSITION REQUIREMENTS
+To ensure proper internal logic performance, it is good prac-
+tice to avoid aligning the falling and rising edges of input sig-
+nals. A delay of at least 1 sec should be incorporated be-
+tween transitions of the Direction, Brake, and/or PWM input
+signals. A conservative approach is be sure there is at least
+500ns delay between the end of the first transition and the
+beginning of the second transition.
+
+
diff --git a/a/puiss-barillet/puiss-barillet.sch b/a/puiss-barillet/puiss-barillet.sch
index 6f7547c..dfbf703 100644
--- a/a/puiss-barillet/puiss-barillet.sch
+++ b/a/puiss-barillet/puiss-barillet.sch
Binary files differ
diff --git a/a/puiss-barillet/spec_turbine.txt b/a/puiss-barillet/spec_turbine.txt
new file mode 100644
index 0000000..c63fdcb
--- /dev/null
+++ b/a/puiss-barillet/spec_turbine.txt
@@ -0,0 +1,5 @@
+Rotor Volts(V) Amps(A) Power(W)
+EDF2020x3 9,6 1,35 12.96
+EDF2020x3 10,8 1,5 16,20
+
+GWS EDF 50H series for 9,6V-10,8V