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-- testbench pour le registre

-- MARCHE

library ieee;
use	ieee.std_logic_1164.all;
use     ieee.std_logic_arith.all;
use     ieee.std_logic_unsigned.all;

use	work.nono_const.all;

entity testreg is
constant adr_w : integer :=10;
constant data_w : integer :=8;
end testreg;

architecture sim1 of testreg is
component regIO
    generic(adr:unsigned);
    port(
	bus_data: inout unsigned ((NB_BIT_DATA - 1) downto 0);
	bus_address: in unsigned ((NB_BIT_ADDRESS - 1) downto 0);
	input: 	in	unsigned((data_w - 1) downto 0);
	output: out	unsigned((data_w - 1) downto 0);
	rw:	in	std_logic;
	load:	in	std_logic;
	ck:	in	std_logic;
	rst:	in	std_logic
	);
end component;

signal bus_address: unsigned((adr_w - 1) downto 0):="0000000000";
signal bus_data: unsigned((data_w - 1) downto 0):="00000000";
signal input: 	 unsigned((data_w - 1) downto 0):="00000000";
signal output: 	unsigned((data_w - 1) downto 0);
signal rw:	std_logic:='0';
signal load:	std_logic:='0';
signal ck:	std_logic:='0';
signal rst:	std_logic:='1';

begin
    R0: regIO
	generic map(adr => "0000000001")
        port map(
	    bus_address=>bus_address,
	    bus_data=>bus_data,
	    input=>input,
	    output=>output,
	    rw=>rw,
	    load=>load,
	    ck=>ck,
	    rst=>rst
	    );

    bus_address <= "0001001100" ,
		"0000000001" after 40 ns;
--		"0000001101" after 100 ns;
--		"0000001100" after 100 ns;

    input <= input + 1 after 3 ns;
    bus_data <= "01010101", "ZZZZZZZZ" after 2 ns;
    rw <= not rw after 11 ns;
    load <= not load after 7 ns;
    ck <= not ck after 5 ns;
    rst <= '0','1' after 1 ns,'0' after 2 ns;
    
end sim1;


configuration cf1 of testreg is
    for sim1
	for all : regIO use entity work.regIO(rtl); end for;
    end for;
end cf1;