summaryrefslogtreecommitdiff
path: root/2004/n/fpga/src/registre/reg_8.vhd
blob: f32f7d91d8d4c4b5a08546fb330c48ee31ad2736 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
-- reg_8.vhd 
-- Eurobot 2004 : APB Team
-- Auteur : Pierre-Andr� Galmes
-- Registre 8 bits.


library IEEE;
use IEEE.STD_LOGIC_1164.all;


entity reg_8 is 
	port (
	rst : in std_logic;
	clk : in std_logic;
	en : in std_logic; -- enable
	input : in std_logic_vector (7 downto 0);
	output : out std_logic_vector (7 downto 0)
	);
end reg_8;

architecture RTL of reg_8 is
begin
	process (rst, clk)
	begin
		if (rst ='1') then
		    output <= x"00";
		elsif (clk'event and clk = '1') then
		    if (en='1') then
			output <= input;
		    end if;
		end if;
	end process;
end RTL;