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-- bch_reg_rw.vhd
-- Eurobot 2004 : APB Team
-- Auteur : Pierre-Andr� Galmes
-- Test de reg_rw.

library ieee;
use	ieee.std_logic_1164.all;
use     ieee.std_logic_arith.all;
use     ieee.std_logic_unsigned.all;

use	work.isa_const.all;
use	work.nono_const.all;


entity bch_reg_rw is
end bch_reg_rw;

architecture sim1 of bch_reg_rw is
    
    component reg_rw
	port (
        clk : in std_logic;
        rst : in std_logic;
        rw  : in std_logic; -- read (ISA_READ) / write (ISA_WRITE)
        enable  : in std_logic;
        data : inout T_DATA;
        data_out : out T_DATA
	);
    end component;

    -- d�finiton des signaux
    signal clk : std_logic := '0';
    signal rst : std_logic;
    signal rw  : std_logic; -- read / write
    signal enable  : std_logic;
    signal data : T_DATA;
    signal data_out : T_DATA;

    constant CK_PERIOD : time := 10 ns;

begin
    U1 : reg_rw port map (
	clk => clk,
	rst => rst,
	rw => rw,
	enable => enable,
	data => data,
	data_out => data_out
	);

    clk <= not clk after CK_PERIOD/2;
    rst <= '1', '0' after CK_PERIOD;
    enable <= 	'0', 
    		'1' after 2*CK_PERIOD,
    		'0' after 3*CK_PERIOD,
    		'1' after 5*CK_PERIOD,
    		'0' after 6*CK_PERIOD;
    rw <= ISA_WRITE, ISA_READ after 3*CK_PERIOD;
    data <=	x"01", 
		x"02" after 3*CK_PERIOD,
    		"ZZZZZZZZ" after 5*CK_PERIOD;
		--x"03" after 5*CK_PERIOD;
end sim1;

configuration cf1_bch_reg_rw of bch_reg_rw is
    for sim1
        for all : reg_rw use entity work.reg_rw(RTL); end for;
    end for;
end cf1_bch_reg_rw;