summaryrefslogtreecommitdiff
path: root/2004/n/fpga/src/portserie/uart/uart_tb.vhd
blob: 1ff67d15cb6fb3242265aa47d38d43e8a01c02e2 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY work;
USE work.all;
--LIBRARY simprim;
--USE simprim.vcomponents.all;
--USE simprim.vpackage.all;

ENTITY TestBench IS
END TestBench;

ARCHITECTURE HTWTestBench OF TestBench IS

COMPONENT uart
   PORT (
         mclkx16     : IN    std_logic;
         read        : IN    std_logic;
         write       : IN    std_logic;
         reset       : IN    std_logic;

         data        : INOUT std_logic_vector(7 downto 0);

         -- receiver input signal, error, and status flags
	 rx          : IN    std_logic;
         rxrdy       : OUT   std_logic;
         parity_err  : OUT   std_logic;
	 framing_err : OUT   std_logic;
	 overrun     : OUT   std_logic;
		
	 -- transmitter output signal and status flag
         tx          : OUT   std_logic;
	 txrdy       : OUT   std_logic
	 );
END COMPONENT;

SIGNAL mclkx16           : std_logic := '1'; -- initialized to 1
SIGNAL read              : std_logic := '1'; -- de-assert read initially
SIGNAL write             : std_logic := '1'; -- de-assert write initially
SIGNAL reset             : std_logic := '1'; -- initialized to 1

SIGNAL data_int          : std_logic_vector(7 downto 0);

-- receiver input signal, error, and status flags

SIGNAL rx                : std_logic;
SIGNAL rxrdy             : std_logic;   
SIGNAL parity_err        : std_logic;
SIGNAL framing_err       : std_logic;
SIGNAL overrun           : std_logic;
		
-- transmitter output signal and status flag

SIGNAL tx                : std_logic;
SIGNAL txrdy             : std_logic;

-- storage of data

SIGNAL data_written      : std_logic_vector(7 downto 0); 
SIGNAL data_received     : std_logic_vector(7 downto 0);

CONSTANT baudrate : time := 500 ns;  -- specify the baudrate for the simulation

	  
BEGIN

-- instantiate UART top level entity into test bench

   U1 : uart port map
      (
       mclkx16     => mclkx16,
       read        => read,
       write       => write,
       reset       => reset,
       data        => data_int,
       rx          => rx,
       rxrdy       => rxrdy,
       parity_err  => parity_err,
       framing_err => framing_err,
       overrun     => overrun,
       tx          => tx,
       txrdy       => txrdy
       );


-------------------------------------------------------------------------------
--                            Begin test bench                               --
-------------------------------------------------------------------------------

-- generate 16 times baudrate clock frequency
-- (mclkx16 = baudrate/16)
-- baudrate/(16*2) used to generate half clock cycle;

mclkx16 <= (Not mclkx16) after (baudrate/(16*2)); 

-- Reset Uart  

reset   <= '0' after 2000 ns;

-- feeding back output from transmitter to the input of receiver

rx      <= tx after 1 ns;


-- core test program

self_check : PROCESS

   -- procedure declaration
   -- declared in process due to assignment to write.
   -- this procedure writes data to the transmitter
   -- timing can be modified to model any CPU write cycle
	
   PROCEDURE write_to_transmitter (data : IN integer) IS
      VARIABLE din : std_logic_vector(7 downto 0);
      BEGIN
         din := conv_std_logic_vector(data,8);
         write <= '0';
         WAIT FOR 100 ns;
         data_int  <= din;
         WAIT FOR 50 ns;
         write        <= '1';
         data_written <= din;
         WAIT FOR 20 ns;
   END write_to_transmitter;


   -- procedure declaration
   -- declared in process due to assignment to read
   -- this procedure reads out data from the receiver
   -- timing can be modified to model any CPU read cycle
	
   PROCEDURE read_out_receiver (data_in : IN std_logic_vector(7 downto 0)) IS
      BEGIN
         read <= '0';
         WAIT FOR 25 ns;
         data_received <= data_in;
         WAIT FOR 75 ns;
         read <= '1';
   END read_out_receiver;


   -- this procedure compares the data sent and received,
   -- and flags for any error it encounters.
   -- Comparison is done just prior to next data transmission,
   -- and after previous received data has been read out.
 
   PROCEDURE compare_data (dataw, datar : IN std_logic_vector(7 downto 0)) IS
      VARIABLE data_wr, data_rv : integer range 0 to 255;
      BEGIN
         data_wr := conv_integer(dataw);
         data_rv := conv_integer(datar);
         ASSERT (data_wr = data_rv) 
         REPORT "Simulation FAILED!!  data_written = "& integer'image(data_wr) &
                "  ===>  data_received = "& integer'image(data_rv)  SEVERITY FAILURE;
      END compare_data ;

      BEGIN
 	 WAIT UNTIL mclkx16'EVENT and mclkx16 = '1';
         IF reset = '0' THEN
            FOR i IN 0 TO 255 LOOP                        -- start test loop;
	       write_to_transmitter(i);                   -- write_to_transmitter procedure call;
	       WAIT UNTIL (rxrdy = '1');                  -- wait for rxrdy;
	       read_out_receiver(data_int);               -- read_out_receiver procedure call;
	       compare_data(data_written, data_received); -- compare_data procedure call;
	    END LOOP;

            REPORT "Simulation OK! Passed all possible combinations successfully!" SEVERITY NOTE;
            REPORT " Simulation OK! Passed all possible combinations successfully! " 
            SEVERITY WARNING;
      END IF;
   END PROCESS;

END HTWTestBench;


-- Configuration simulation

configuration TestBench1 of TestBench is
  for HTWTestBench
     for U1: UART use entity work.uart(TOP);
     end for;
  end for;
end TestBench1;