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-- VHDL Test Bench Created from source file txmit.vhd -- 03:08:15 03/11/2004
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends 
-- that these types always be used for the top-level I/O of a design in order 
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;

ENTITY txmit_bch_txmit_vhd_tb IS
END txmit_bch_txmit_vhd_tb;

ARCHITECTURE behavior OF txmit_bch_txmit_vhd_tb IS 

	COMPONENT txmit
	PORT(
		MCLKX16 : IN std_logic;
		WRITE : IN std_logic;
		RESET : IN std_logic;
		DATA : IN std_logic_vector(7 downto 0);          
		TX : OUT std_logic;
		TXRDY : OUT std_logic
		);
	END COMPONENT;

	SIGNAL clk :  std_logic:='0';
	SIGNAL WRITE :  std_logic:='0';
	SIGNAL rst :  std_logic:='0';
	SIGNAL DATA :  std_logic_vector(7 downto 0):=(others => '0');
	SIGNAL TX :  std_logic:='0';
	SIGNAL TXRDY :  std_logic:='0';

BEGIN

	uut: txmit PORT MAP(
		MCLKX16 => clk,
		WRITE => WRITE,
		RESET => rst,
		DATA => DATA,
		TX => TX,
		TXRDY => TXRDY
	);

--	data <= std_logic_vector(unsigned(data) + 1) after 80 ns;
	data <= "01010101","10101010" after 2000 ns;
	rst<='1' , '0' after 10 ns;
	clk <= not clk after 1 ns;
	write <= not write after 400 ns;

END;