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entity modele is
    generic (
	-- adresses des diff�rents registres du module.
	A_REG1 : T_ADDRESS;
	A_REG2 : T_ADDRESS;
	A_REG3 : T_ADDRESS
	-- si autre choses � d�clarer...
    );
    port (
	rst : in std_logic;
	clk : in std_logic;
	rw  : in std_logic; -- read (0) / write (1)
	bus_data : inout T_DATA;
	bus_address : in T_ADDRESS