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-- fifodriver.vhd
-- Eurobot 2004 : APB Team
-- Auteur : Pierre Prot

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use	work.nono_const.all;

library UNISIM;
use UNISIM.VComponents.all;

-- pilote de fifo
entity fifodriver is
    port(
	clk: in std_logic;
	rst: in std_logic;
	readreq: in std_logic;
	writereq: in std_logic;
	din: IN std_logic_VECTOR(7 downto 0);
	dout: OUT std_logic_VECTOR(7 downto 0);
	dready: out std_logic;
	full: OUT std_logic;
	empty: OUT std_logic;
	data_count: OUT std_logic_VECTOR(1 downto 0)
	);
end fifodriver;

-- arch
architecture rtl of fifodriver is
component sfifo
	port (
	clk: IN std_logic;
	sinit: IN std_logic;
	din: IN std_logic_VECTOR(7 downto 0);
	wr_en: IN std_logic;
	rd_en: IN std_logic;
	dout: OUT std_logic_VECTOR(7 downto 0);
	full: OUT std_logic;
	empty: OUT std_logic;
	rd_ack: OUT std_logic;
	wr_ack: OUT std_logic;
	rd_err: OUT std_logic;
	wr_err: OUT std_logic;
	data_count: OUT std_logic_VECTOR(1 downto 0));
end component;



signal	wr_en:std_logic;
signal	rd_en:std_logic;
signal	state_read:integer:=0;
signal	state_write:integer:=0;

signal	rd_ack:std_logic;
signal	wr_ack:std_logic;
signal	rd_err:std_logic;
signal	wr_err:std_logic;


begin
  -- Component Instantiation
fifo0 : sfifo
		port map (
			clk => clk,
			sinit => rst,
			din => din,
			wr_en => wr_en,
			rd_en => rd_en,
			dout => dout,
			full => full,
			empty => empty,
			rd_ack => rd_ack,
			wr_ack => wr_ack,
			rd_err => rd_err,
			wr_err => wr_err,
			data_count => data_count);


  -- process
	read:process(clk)
	begin
		if(rst='1') then
			rd_en<='0';
		elsif(clk'event and clk='0') then
			rd_en<='0';
			dready<='0';
			case state_read is
			when 0 => 	if(readreq='1') then
								state_read<=1;
								rd_en<='1';
							end if;
			when 1 => 	state_read<=2;
							dready<='1';
			when 2 => 	if(readreq='0') then
								state_read<=0;
							else
								state_read<=3;
							end if;
			when 3 =>	if(readreq='0') then
								state_read<=0;
							end if;
			when others => null;	
			end case;			
		end if;
	end process;

	write:process(clk)
	begin
		if(rst='1') then
			wr_en<='0';
		elsif(clk'event and clk='0') then
			wr_en<='0';
			case state_write is
			when 0 => 	if(writereq='1') then
								state_write<=1;
								wr_en<='1';
							end if;
			when 1 => 	state_write<=2;
			when 2 => 	if(writereq='0') then
								state_write<=0;
							end if;
			when others => null;	
			end case;			
		end if;
	end process;

end rtl;