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-- modele.vhd
-- Eurobot 2004 : APB Team
-- Auteur : Pierre-Andr� Galmes
-- Fichier mod�le pour la d�claration de module.

library ieee;
use	ieee.std_logic_1164.all;
use     ieee.std_logic_arith.all;
use     ieee.std_logic_unsigned.all;

use	work.nono_const.all;

entity modele is
    generic (
	-- adresses des diff�rents registres du module.
	A_REG1 : T_ADDRESS := A_REG_IO_DIRECTION;
	A_REG2 : T_ADDRESS := A_REG_IO_DATA;
	A_REG3 : T_ADDRESS := A_REG_IO_INTERRUPT_MASK
	-- si autre choses � d�clarer...
    );
    port (
	rst : in std_logic;
	clk : in std_logic;
	
	-- XXX : savoir si read = 0 ou 1 !!
	rw  : in std_logic; -- read (0) / write (1)
	
	bus_data : inout unsigned ((NB_BIT_DATA - 1) downto 0);
	bus_address : in unsigned ((NB_BIT_ADDRESS - 1) downto 0)
    );
end entity;

architecture test_modele of modele is
begin
    process (rst, clk)
    begin
	if (rst = '1') then
	    bus_data <= x"00";
	elsif (clk'event and clk = '1') then
	    if (bus_address = A_REG1) then
		bus_data <= x"01";
	    else 
		if (bus_address = A_REG2) then
		    bus_data <= x"02";
		elsif (bus_address = A_REG3) then
		    bus_data <= x"03";
		end if;
	    end if;
	end if;
    end process;
end test_modele;