summaryrefslogtreecommitdiff
path: root/2004/n/fpga/src/modele/bch_modele.vhd
blob: 8ee34e328fbeb3d26a1d075aa7ed4d8ab243d197 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
-- modele.vhd
-- Eurobot 2004 : APB Team
-- Auteur : Pierre-Andr� Galmes
-- Fichier mod�le pour la d�claration de module.

library ieee;
use	ieee.std_logic_1164.all;
use     ieee.std_logic_arith.all;
use     ieee.std_logic_unsigned.all;

use	work.nono_const.all;


entity bch_modele is
end bch_modele;

architecture sim1 of bch_modele is
    
    component modele
	port (
	    rst : in std_logic;
	    clk : in std_logic;
	    rw  : in std_logic; -- read (0) / write (1)
	    bus_data : inout T_DATA;
	    -- chaque registre se voit administrer un chip select.
	    cs_reg0 : in std_logic; -- chip select
	    cs_reg1 : in std_logic;
	    cs_reg2 : in std_logic
    );
    end component;

    -- d�finiton des signaux
    signal rst : std_logic;
    signal clk : std_logic := '0';
    signal rw  : std_logic; -- read / write
    signal bus_data : T_DATA;
    signal cs_reg0 : std_logic := '0'; -- chip select
    signal cs_reg1 : std_logic := '0';
    signal cs_reg2 : std_logic := '0';

begin
    U1 : modele
	port map (		
	    rst => rst,
	    clk => clk,
	    rw => rw,
	    bus_data => bus_data,
	    cs_reg0 => cs_reg0,
	    cs_reg1 => cs_reg1,
	    cs_reg2 => cs_reg2
	);

    rst <= '1', '0' after CK_PERIOD;
    clk <= not clk after (CK_PERIOD/2);
    rw <= '0';
    cs_reg0 <= '1' after CK_PERIOD,
	       '0' after 3*CK_PERIOD;
    cs_reg1 <= '1' after 4*CK_PERIOD,
	       '0' after 7*CK_PERIOD;
    cs_reg2 <= '1' after 8*CK_PERIOD,
	       '0' after 10*CK_PERIOD;
    
end sim1;

configuration cf1_bch_modele of bch_modele is
    for sim1
        for all : modele use entity work.modele(test_modele); end for;
    end for;
end cf1_bch_modele;