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path: root/2004/n/fpga/src/gpio/gpio.vhd
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-- gpio.vhd
-- Eurobot 2004 : APB Team
-- Auteur : Pierre-Andr� Galmes
-- Fichier mod�le pour la d�claration de module.

library ieee;
use	ieee.std_logic_1164.all;
use     ieee.std_logic_arith.all;
use     ieee.std_logic_unsigned.all;

use	work.nono_const.all;

entity gpio is
    generic (
	A_REG_DATA_WRITE : T_ADDRESS;
        A_REG_DATA_READ : T_ADDRESS;
        A_REG_DIRECTION : T_ADDRESS;
        A_REG_INTERRUPT_MASK : T_ADDRESS
    );
    port(
	rst : in std_logic;
	clk_i : in std_logic;	-- clock du bus isa
	clk_m : in std_logic;	-- master clock
	rw  : in std_logic; -- read (0) / write (1) TODO ??
	interrupt : out std_logic;
	bus_address : in T_ADDRESS;
	bus_data : inout T_DATA;
	io_output : inout T_DATA
    );
end entity;

architecture RTL of gpio is

-- D�finition des composants utilis�s.

-- D�codeur d'addresses.
component decodeur is
    generic (
        -- adresses des diff�rents registres du module.
        A_REG0 : T_ADDRESS;
        A_REG1 : T_ADDRESS;
        A_REG2 : T_ADDRESS;
        A_REG3 : T_ADDRESS
    );
    port (
        bus_address : in T_ADDRESS;
        enable0 : out std_logic;
        enable1 : out std_logic;
        enable2 : out std_logic;
        enable3 : out std_logic
    );
end component;

-- Registre.
component reg_rw is
    port (
        clk : in std_logic;
        rst : in std_logic;
        rw  : in std_logic; -- read (ISA_READ) / write (ISA_WRITE)
        enable  : in std_logic;
        data : inout T_DATA;
        data_out : out T_DATA -- data courant
    );
end component;

-- ET bit � bit  � sortie trhee state.
component gpio_direction is
    port (
        direction_mask : in T_DATA;
        data_in : in T_DATA;
        data_out : out T_DATA
    );
end component;

-- d�tecteur d'interruption 8 bits.
component gpio_it_detect is
    port (
        clk : in std_logic;
        rst : in std_logic;
        data_in : in T_DATA;
        it_mask : in T_DATA;
        it_detected : out std_logic
    );
end component;

-- Composant three-state.
component tristate is
    port (
        enable  : in std_logic;
        data_in : in T_DATA;
        data_out : out T_DATA
    );
end component;

-- d�finition des signaux.
-- clk, rst... sont d�finis dans l'entity du GPIO.
--
signal en_reg_direction : std_logic; 
signal en_reg_it_mask : std_logic; 
signal en_reg_data : std_logic; 
signal en_read_output : std_logic; 
--
signal bus_direction_mask : T_DATA;
signal bus_it_mask : T_DATA;
signal bus_reg_data : T_DATA;

begin

-- Mapping des composants.
decod : decodeur 
generic map (
    A_IO1_REG_DATA,
    A_IO1_REG_DIRECTION,
    A_IO1_REG_INTERRUPT_MASK,
    A_IO1_READ_OUTPUT
)
port map (
    bus_address, 
    en_reg_data, 
    en_reg_direction, 
    en_reg_it_mask, 
    en_read_output
); 
	
--
Reg_direction_mask : reg_rw 
port map (
    clk_m, 
    rst, 
    rw, 
    en_reg_direction, 
    bus_data, 
    bus_direction_mask
);
  
--  
Reg_data : reg_rw 
port map (
    clk_m, 
    rst, 
    rw, 
    en_reg_data, 
    bus_data, 
    bus_reg_data
);

--
Reg_it_mask : reg_rw 
port map (
    clk_m, 
rst, 
rw, 
en_reg_data, 
bus_data, 
bus_it_mask
);

--
read_output : tristate 
port map (
    en_read_output, 
    io_output, 
    bus_data
);

--
gest_direction : gpio_direction 
port map (
    bus_direction_mask, 
    bus_reg_data, 
    io_output
);

--
it_detector : gpio_it_detect 
port map (
    clk_m, 
    rst, 
    io_output, 
    bus_it_mask, 
    interrupt
);

end RTL;