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-- decodeur.vhd
-- Eurobot 2004 : APB Team
-- Auteur : Pierre-Andr� Galmes
-- Fichier mod�le pour la d�claration de module.

library ieee;
use	ieee.std_logic_1164.all;
use     ieee.std_logic_arith.all;
use     ieee.std_logic_unsigned.all;

use	work.nono_const.all;


entity bch_decodeur is
end bch_decodeur;

architecture sim1 of bch_decodeur is
    
    component decodeur
	generic (
	    -- adresses des diff�rents registres du module.
	    A_REG0 : T_ADDRESS;
	    A_REG1 : T_ADDRESS;
	    A_REG2 : T_ADDRESS;
	    A_REG3 : T_ADDRESS
	    -- si autre choses � d�clarer...
	);
	port (
	    -- TODO : utile la clock ?
	    --clk : in std_logic;
	    bus_address : in T_ADDRESS;
	    enable0 : out std_logic;
	    enable1 : out std_logic;
	    enable2 : out std_logic;
	    enable3 : out std_logic
	);
    end component;

    -- d�finiton des signaux
    --signal clk : std_logic := '0';
    signal bus_address : T_ADDRESS;
    signal enable0 : std_logic;
    signal enable1 : std_logic;
    signal enable2 : std_logic;
    signal enable3 : std_logic;

begin
    U1 : decodeur
    	generic map (
	    -- D�finition des addresses.
	    A_REG0 => A_IO1_REG_DATA,
	    A_REG1 => A_IO1_REG_DIRECTION,
	    A_REG2 => A_IO1_REG_INTERRUPT_MASK,
	    A_REG3 => A_IO1_READ_OUTPUT
	)
	port map (		
	    bus_address => bus_address,
	    enable0 => enable0,
	    enable1 => enable1,
	    enable2 => enable2,
	    enable3 => enable3
	);

    --clk <= not clk after (CK_PERIOD/2);
    bus_address <=	A_IO1_REG_DIRECTION, 
			A_IO1_READ_OUTPUT after 3*CK_PERIOD,
			A_IO1_REG_INTERRUPT_MASK	after 5*CK_PERIOD,
			A_IO1_REG_DATA after 7*CK_PERIOD;
end sim1;

configuration cf1_bch_decodeur of bch_decodeur is
    for sim1
        for all : decodeur use entity work.decodeur(RTL); end for;
    end for;
end cf1_bch_decodeur;