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path: root/2004/n/fpga/src/FPGA_BOARD/Project Outputs for Protel/PC104_PCB_2.8.RUL
blob: a0ae37b5f93e82fdaf6cd880c4f1ca91b5c1d096 (plain)
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DRC Rules Export File for PCB: C:\travail\Protel\PC104_PCB_2.8.PcbDoc
RuleKind=Width|RuleName=Width_3.95V|Scope=Board|Minimum=10,00
RuleKind=Clearance|RuleName=Clearance|Scope=Board|Minimum=7,87
RuleKind=Width|RuleName=Width|Scope=Board|Minimum=7,87
RuleKind=SolderMaskExpansion|RuleName=SolderMaskExpansion_1|Scope=Board|Minimum=4,00
RuleKind=SolderMaskExpansion|RuleName=SolderMaskExpansion|Scope=Board|Minimum=4,00
RuleKind=ShortCircuit|RuleName=ShortCircuit|Scope=Board|Allowed=0