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path: root/2004/n/fpga/src/FPGA_BOARD/Project Outputs for Protel/PC104_PCB_2.8.LDP
blob: 74aa37322978455e152719416329dd6fa30a3cd2 (plain)
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Layer Pairs Export File for PCB: C:\travail\Protel\PC104_PCB_2.8.PcbDoc
LayersSetName=Top_Bot_Thru_Holes|DrillFile=txt|LayerPairs=gtl,gbl