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Diffstat (limited to '2004/n/fpga/src/registre/registre.vhd')
-rw-r--r--2004/n/fpga/src/registre/registre.vhd8
1 files changed, 5 insertions, 3 deletions
diff --git a/2004/n/fpga/src/registre/registre.vhd b/2004/n/fpga/src/registre/registre.vhd
index 2b5301c..219e1f1 100644
--- a/2004/n/fpga/src/registre/registre.vhd
+++ b/2004/n/fpga/src/registre/registre.vhd
@@ -47,7 +47,7 @@ architecture rtl of regIO is
signal REG : T_DATA :=(others => '0');
begin
- p_w:process(ck,load,input,rst,rw)
+ p_w:process(ck,load,input,rst)
begin
if(rst='1') then
REG<=(others => '0');
@@ -60,12 +60,14 @@ begin
end if;
-- chargement : prioritaire sur l'écriture via le bus
- if(load='1' and not(ck='1' and rw='1')) then
+-- if(load='1' and not(ck='1' and rw='1')) then
+ if(load='1') then
REG<=input;
end if;
end process;
- bus_data<=REG when (rw='1' and cs='1' and ck='1' and rst='0') else (others => 'Z');
+ bus_data<=REG when (rw='1' and cs='1' and rst='0') else (others => 'Z');
+
output<=REG;
end rtl;