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Diffstat (limited to '2004/n/fpga/src/registre/reg_rw.vhd')
-rw-r--r--2004/n/fpga/src/registre/reg_rw.vhd8
1 files changed, 8 insertions, 0 deletions
diff --git a/2004/n/fpga/src/registre/reg_rw.vhd b/2004/n/fpga/src/registre/reg_rw.vhd
index 25d645f..764eb0d 100644
--- a/2004/n/fpga/src/registre/reg_rw.vhd
+++ b/2004/n/fpga/src/registre/reg_rw.vhd
@@ -44,11 +44,19 @@ begin
elsif (clk'event and clk = '1') then
if (enable = '1' and rw = ISA_WRITE) then
REG <= data;
+-- end if;
+ --else
+ -- if (enable = '1' and rw = ISA_READ) then
+ -- data <= REG;
+ -- else
+ -- data <= (others =>'Z');
+ -- end if;
end if;
end if;
end process;
-- partie combinatoire.
+ -- commenter ligne suivante pour version 1
data <= REG when (enable = '1' and rw = ISA_READ) else (others => 'Z');
data_out <= REG;