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-rw-r--r--2004/n/fpga/src/portserie/clockgene/clockgene.vhd16
-rw-r--r--2004/n/fpga/src/portserie/fifo/bch_fifodriver.vhd12
-rw-r--r--2004/n/fpga/src/portserie/fifo/bch_sfifo.vhd6
-rw-r--r--2004/n/fpga/src/portserie/fifo/fifo.npl9
-rw-r--r--2004/n/fpga/src/portserie/fifo/fifodriver.vhd2
-rw-r--r--2004/n/fpga/src/portserie/fifo/sfifo.xco20
-rw-r--r--2004/n/fpga/src/portserie/portserie/bch_txserie.vhd12
-rw-r--r--2004/n/fpga/src/portserie/portserie/portserie.npl2
-rw-r--r--2004/n/fpga/src/portserie/portserie/sfifo.xco5
-rw-r--r--2004/n/fpga/src/portserie/portserie/txserie.vhd21
-rw-r--r--2004/n/fpga/src/portserie/rxserie/bch_rxserie.vhd24
-rw-r--r--2004/n/fpga/src/portserie/rxserie/rxserie.npl14
-rw-r--r--2004/n/fpga/src/portserie/rxserie/rxserie.vhd13
-rw-r--r--2004/n/fpga/src/portserie/rxserie/sfifo.xco9
-rw-r--r--2004/n/fpga/src/portserie/uart/txmit.vhd14
15 files changed, 104 insertions, 75 deletions
diff --git a/2004/n/fpga/src/portserie/clockgene/clockgene.vhd b/2004/n/fpga/src/portserie/clockgene/clockgene.vhd
index b98a6b3..554d561 100644
--- a/2004/n/fpga/src/portserie/clockgene/clockgene.vhd
+++ b/2004/n/fpga/src/portserie/clockgene/clockgene.vhd
@@ -9,8 +9,7 @@
library ieee;
use ieee.std_logic_1164.all;
-use ieee.std_logic_arith.all;
-use ieee.std_logic_unsigned.all;
+use ieee.std_logic_arith.all;
use work.nono_const.all;
-- pour la valeur de DIVIS_CK_SERIAL
@@ -31,9 +30,8 @@ port(
);
end clockgene;
-
architecture rtl of clockgene is
-signal compteur:std_logic_vector(10 downto 0):=(others=>'0');
+signal compteur:std_logic_vector(9 downto 0):="0000000000";
signal div_param:integer; -- le diviseur paramétrable
signal clr:std_logic;
@@ -48,7 +46,7 @@ begin
when "01" => div_param <= (DIVIS_CK_SERIAL*6); -- 19200 * 6 =115200
when "10" => div_param <= (DIVIS_CK_SERIAL*2); -- 57600 * 2 =115200
when "11" => div_param <= DIVIS_CK_SERIAL; -- 115200 * 1=115200
- when others => null;
+ when others => div_param <= (DIVIS_CK_SERIAL*12); -- 9600 * 12 =115200
end case;
end process;
@@ -57,13 +55,13 @@ begin
begin
if(clr='1') then
ckout<='0';
- compteur<=(others=>'0');
+ compteur<=conv_std_logic_vector(div_param, 10);
elsif(ckin'event and ckin='1') then
- if(compteur = div_param) then
+ if(compteur = "0000000000") then
ckout<='1';
- compteur<=(others=>'0');
+ compteur<=conv_std_logic_vector(div_param, 10);
else
- compteur <= compteur + 1;
+ compteur <= conv_std_logic_vector( (unsigned(compteur) - 1),10);
ckout<='0';
end if;
end if;
diff --git a/2004/n/fpga/src/portserie/fifo/bch_fifodriver.vhd b/2004/n/fpga/src/portserie/fifo/bch_fifodriver.vhd
index a109693..94fa9a2 100644
--- a/2004/n/fpga/src/portserie/fifo/bch_fifodriver.vhd
+++ b/2004/n/fpga/src/portserie/fifo/bch_fifodriver.vhd
@@ -41,7 +41,7 @@ signal data_count: std_logic_VECTOR(1 downto 0);
BEGIN
-Inst_fifodriver: fifodriver PORT MAP(
+uut: fifodriver PORT MAP(
clk => clk,
rst => rst,
readreq => readreq,
@@ -55,11 +55,11 @@ Inst_fifodriver: fifodriver PORT MAP(
);
- din <= std_logic_vector(unsigned(din) + 1) after 8 ns;
- rst<='1' , '0' after 10 ns;
- clk <= not clk after 1 ns;
- writereq <= not writereq after 13 ns;
- readreq <= not readreq after 17 ns;
+ din <= std_logic_vector(unsigned(din) + 1) after 400 ns;
+ rst<='1' , '0' after 510 ns;
+ clk <= not clk after 25 ns;
+ writereq <= not writereq after 700 ns;
+ readreq <= not readreq after 900 ns;
diff --git a/2004/n/fpga/src/portserie/fifo/bch_sfifo.vhd b/2004/n/fpga/src/portserie/fifo/bch_sfifo.vhd
index a3d930d..68b409f 100644
--- a/2004/n/fpga/src/portserie/fifo/bch_sfifo.vhd
+++ b/2004/n/fpga/src/portserie/fifo/bch_sfifo.vhd
@@ -44,7 +44,7 @@ signal wr_err: std_logic;
-- Component Instantiation
-U0 : sfifo
+uut : sfifo
port map (
clk => clk,
sinit => sinit,
@@ -60,11 +60,9 @@ U0 : sfifo
wr_err => wr_err,
data_count => data_count);
-
-
din <= std_logic_vector(unsigned(din) + 1) after 8 ns;
sinit <= '1' , '0' after 10 ns;
clk <= not clk after 3 ns;
rd_en <= '0' , '1' after 50 ns;
- END;
+ END behavior;
diff --git a/2004/n/fpga/src/portserie/fifo/fifo.npl b/2004/n/fpga/src/portserie/fifo/fifo.npl
index c8ba229..81fdd87 100644
--- a/2004/n/fpga/src/portserie/fifo/fifo.npl
+++ b/2004/n/fpga/src/portserie/fifo/fifo.npl
@@ -20,13 +20,16 @@ DEVGENERATEDSIMULATIONMODEL VHDL
GENERATEDSIMULATIONMODELTIME 0
STIMULUS bch_afifo.vhd
SOURCE fifodriver.vhd
-STIMULUS bch_fifodriver.vhd
SOURCE ..\..\modele\nono_const.vhd
-SOURCE sfifo.xco
STIMULUS bch_sfifo.vhd
+SOURCE sfifo.xco
+STIMULUS bch_fifodriver.vhd
[Normal]
p_CompxlibTargetSimulator=xstvhd, spartan2, Design.t_compLibraries, 1078952453, ModelSim SE
[STATUS-ALL]
-bch_fifodriver.vhd.testbenchRpt=ERRORS,0
+fifodriver.ngcFile=WARNINGS,1079734309
+fifodriver.ngdFile=WARNINGS,1079734329
+fifodriver.postMapVHDLSimModel=WARNINGS,1079734429
+sfifo.ngcFile=ERRORS,0
[STRATEGY-LIST]
Normal=True
diff --git a/2004/n/fpga/src/portserie/fifo/fifodriver.vhd b/2004/n/fpga/src/portserie/fifo/fifodriver.vhd
index 3830e93..11d1955 100644
--- a/2004/n/fpga/src/portserie/fifo/fifodriver.vhd
+++ b/2004/n/fpga/src/portserie/fifo/fifodriver.vhd
@@ -61,7 +61,7 @@ signal wr_err:std_logic;
begin
-- Component Instantiation
-U0 : sfifo
+fifo0 : sfifo
port map (
clk => clk,
sinit => rst,
diff --git a/2004/n/fpga/src/portserie/fifo/sfifo.xco b/2004/n/fpga/src/portserie/fifo/sfifo.xco
index 306f531..236a635 100644
--- a/2004/n/fpga/src/portserie/fifo/sfifo.xco
+++ b/2004/n/fpga/src/portserie/fifo/sfifo.xco
@@ -5,13 +5,13 @@
# ExpandedProjectPath = D:\vhdl\robot\carte_fpga\src\portserie\fifo
# OverwriteFiles = true
# Core name: sfifo
-# Number of Primitives in design: 120
+# Number of Primitives in design: 87
# Number of CLBs used in design cannot be determined when there is no RPMed logic
# Number of Slices used in design cannot be determined when there is no RPMed logic
-# Number of LUT sites used in design: 70
-# Number of LUTs used in design: 46
-# Number of REG used in design: 24
-# Number of SRL16s used in design: 24
+# Number of LUT sites used in design: 43
+# Number of LUTs used in design: 35
+# Number of REG used in design: 22
+# Number of SRL16s used in design: 8
# Number of Distributed RAM primitives used in design: 0
# Number of Block Memories used in design: 0
# Number of Dedicated Multipliers used in design: 0
@@ -25,18 +25,18 @@ SET FormalVerification = None
SET OutputProducts = ImpNetlist ASYSymbol VHDLSim VerilogSim
SELECT Synchronous_FIFO Spartan2 Xilinx,_Inc. 4.0
CSET data_width = 8
-CSET read_error_sense = active_high
+CSET read_error_sense = Active_Low
CSET read_error_flag = true
CSET write_acknowledge_flag = true
CSET write_error_flag = true
CSET data_count = true
CSET memory_type = Distributed_Memory
-CSET read_acknowledge_sense = active_high
+CSET read_acknowledge_sense = Active_Low
CSET component_name = sfifo
-CSET fifo_depth = 32
+CSET fifo_depth = 16
CSET read_acknowledge_flag = true
CSET data_count_width = 2
-CSET write_error_sense = active_high
-CSET write_acknowledge_sense = active_high
+CSET write_error_sense = Active_Low
+CSET write_acknowledge_sense = Active_Low
GENERATE
diff --git a/2004/n/fpga/src/portserie/portserie/bch_txserie.vhd b/2004/n/fpga/src/portserie/portserie/bch_txserie.vhd
index 3400854..25fadff 100644
--- a/2004/n/fpga/src/portserie/portserie/bch_txserie.vhd
+++ b/2004/n/fpga/src/portserie/portserie/bch_txserie.vhd
@@ -22,6 +22,7 @@ component txserie
rw : in std_logic; -- read (0) / write (1)
bus_data : inout T_DATA:=(others => 'Z');
clk: in std_logic;
+ clk_ref: in std_logic;
txout: out std_logic;
minIRQ: out std_logic;
csData : in std_logic;
@@ -35,6 +36,7 @@ end component;
signal simclk:std_logic:='0';
signal rst : std_logic;
signal clk : std_logic;
+signal clk_ref : std_logic:='0';
signal rw : std_logic;
signal bus_data : T_DATA:=(others => 'Z');
signal masterck: std_logic:='0';
@@ -44,18 +46,19 @@ signal csData : std_logic;
signal csConfig : std_logic;
signal csFlag : std_logic;
-signal state:integer:=-3;
+signal state:integer:=-30;
begin
- U1 : txserie
+ UUT : txserie
port map(
rst => rst,
bus_clk => clk,
rw =>rw,
bus_data => bus_data,
clk => masterck,
+ clk_ref => clk_ref,
txout => txout,
minIRQ => minirq,
csData => csData,
@@ -66,6 +69,7 @@ begin
rst<='1','0' after 5 ns;
simclk<= not simclk after 10 ns;
masterck<= not masterck after 3 ns;
+ clk_ref <= not clk_ref after 10 ns;
combi:process(state)
begin
@@ -77,10 +81,10 @@ begin
csFlag <= '0';
case state is
- when 1 => bus_data<="00010110";
+ when 1 => bus_data<="01110111";
csConfig<='1';
rw<='0';
- when 2 => bus_data<="00010110";
+ when 2 => bus_data<="01110111";
csConfig<='1';
rw<='0';
clk<='1';
diff --git a/2004/n/fpga/src/portserie/portserie/portserie.npl b/2004/n/fpga/src/portserie/portserie/portserie.npl
index 1743fbf..b293bd4 100644
--- a/2004/n/fpga/src/portserie/portserie/portserie.npl
+++ b/2004/n/fpga/src/portserie/portserie/portserie.npl
@@ -30,7 +30,9 @@ SOURCE ..\fifo\sfifo.xco
STIMULUS bch_txmit.vhd
STIMULUS ..\fifo\bch_fifodriver.vhd
SOURCE ..\clockgene\clockgene.vhd
+STIMULUS bch_clockgene.vhd
[Normal]
+p_CompxlibOutputDir=xstvhd, spartan2, Design.t_compLibraries, 1079779592, D:\xilinx\vhdl\src
p_CompxlibTargetSimulator=xstvhd, spartan2, Design.t_compLibraries, 1078871494, ModelSim SE
[STRATEGY-LIST]
Normal=True
diff --git a/2004/n/fpga/src/portserie/portserie/sfifo.xco b/2004/n/fpga/src/portserie/portserie/sfifo.xco
index a2badbd..cc7276e 100644
--- a/2004/n/fpga/src/portserie/portserie/sfifo.xco
+++ b/2004/n/fpga/src/portserie/portserie/sfifo.xco
@@ -18,11 +18,12 @@
# Number of HU_SETs used: 0
#
SET BusFormat = BusFormatAngleBracketNotRipped
+SET SimulationOutputProducts = VHDL
SET XilinxFamily = Spartan2
-SET OutputOption = OutputProducts
+SET OutputOption = DesignFlow
+SET DesignFlow = VHDL
SET FlowVendor = Foundation_iSE
SET FormalVerification = None
-SET OutputProducts = ImpNetlist ASYSymbol VHDLSim VerilogSim
SELECT Synchronous_FIFO Spartan2 Xilinx,_Inc. 4.0
CSET data_width = 8
CSET read_error_sense = Active_Low
diff --git a/2004/n/fpga/src/portserie/portserie/txserie.vhd b/2004/n/fpga/src/portserie/portserie/txserie.vhd
index b1ceb53..2b94529 100644
--- a/2004/n/fpga/src/portserie/portserie/txserie.vhd
+++ b/2004/n/fpga/src/portserie/portserie/txserie.vhd
@@ -46,6 +46,7 @@ entity txserie is
rw : in std_logic; -- read (0) / write (1)
bus_data : inout T_DATA:=(others => 'Z');
clk: in std_logic;
+ clk_ref: in std_logic;
txout: out std_logic;
minIRQ: out std_logic;
csData : in std_logic;
@@ -115,16 +116,15 @@ signal txck: std_logic;
signal geneck:std_logic;
signal txload: std_logic:='0';
-signal loadingtx: std_logic:='0';
signal confreg: T_DATA:="00000000";
signal flagreg: T_DATA:="00000000";
signal inter_data: T_DATA;
-signal inter_fifo_bus: T_DATA;
+--signal inter_fifo_bus: T_DATA;
signal txready: std_logic:='1';
signal fifodready :std_logic;
-signal state:integer:=1;
-signal state_next:integer:=1;
+--signal state:integer:=1;
+--signal state_next:integer:=1;
signal state_txload:integer:=0;
signal dummy : T_DATA :=(others =>'0');
@@ -135,7 +135,7 @@ signal un: std_logic :='1';
begin
CLOCK1 : clockgene port map(
rst => rst,
- ckin=>geneck,
+ ckin=>clk_ref,--geneck,
ckout=>txck,
param=>confreg(1 downto 0));
@@ -185,7 +185,7 @@ RFLAG : regIO port map(
-- signaux
-- config
-geneck <= (confreg(4) and clk); -- On/Off et masterck
+geneck <= (clk_ref);-- and confreg(4); -- On/Off et masterck
fifopurge <= '1' when (rst='1') else confreg(3); -- reset or purge
-- flags
@@ -208,22 +208,29 @@ begin
state_txload <= 3;
elsif(fifodready='1') then
state_txload <= 1;
+ else
+ state_txload <= 0;
end if;
when 1 => if(txready='1') then
state_txload <= 2;
txload <= '1';
+ else
+ state_txload <= 1;
end if;
when 2 => if(txready='0') then
state_txload <= 0;
else
txload <= '1';
+ state_txload <= 2;
end if;
when 3 => if(fifodready='1') then
state_txload <= 2;
txload <= '1';
+ else
+ state_txload <= 3;
end if;
- when others => null;
+ when others => state_txload <= 0;
end case;
end process;
diff --git a/2004/n/fpga/src/portserie/rxserie/bch_rxserie.vhd b/2004/n/fpga/src/portserie/rxserie/bch_rxserie.vhd
index ec71a5c..b575b9d 100644
--- a/2004/n/fpga/src/portserie/rxserie/bch_rxserie.vhd
+++ b/2004/n/fpga/src/portserie/rxserie/bch_rxserie.vhd
@@ -20,14 +20,15 @@ use work.isa_const.all;
rw : in std_logic; -- read (0) / write (1)
bus_data : inout T_DATA;
clk: in std_logic;
+ clk_ref: in std_logic;
rxin: in std_logic;
irqFIFO: out std_logic;
irqRX: out std_logic;
+ irqERR: out std_logic;
csData : in std_logic;
csConfig : in std_logic;
csFlag : in std_logic);
END COMPONENT;
-
signal rst: std_logic;
@@ -36,9 +37,11 @@ signal rw: std_logic;
signal bus_data: T_DATA;
signal data_received: T_DATA;
signal clk: std_logic:='0';
+signal clk_ref: std_logic:='0';
signal rxin: std_logic:='1';
signal irqFIFO: std_logic;
signal irqRX: std_logic;
+signal irqERR: std_logic;
signal csData: std_logic;
signal csConfig: std_logic;
signal csFlag: std_logic;
@@ -47,34 +50,35 @@ signal csFlag: std_logic;
BEGIN
- Inst_rxserie: rxserie PORT MAP(
+ uut: rxserie PORT MAP(
rst => rst,
bus_clk => bus_clk,
rw => rw,
bus_data => bus_data,
clk => clk,
+ clk_ref => clk_ref,
rxin => rxin,
irqFIFO => irqFIFO,
irqRX => irqRX,
+ irqERR => irqERR,
csData => csData,
csConfig => csConfig,
csFlag => csFlag
);
--- baudrate/(16*2) used to generate half clock cycle;
+-- master clock
clk <= (Not clk) after (CK_PERIOD/2);
-- Reset Uart
rst <= '1','0' after (10*CK_PERIOD);
--- feeding back output from transmitter to the input of receiver
-rxin <= not rxin after 12 us;
+-- baudrate/(16*2) used to generate half clock cycle;
+clk_ref <= (not clk_ref) after 135 ns; --1,8432MHz
+-- feeding back output from transmitter to the input of receiver
+rxin <= not rxin after 15751 ns;
--- csData => csData,
--- csConfig => csConfig,
--- csFlag => csFlag
check:process
@@ -124,12 +128,12 @@ begin
csData<='1';
read_bus;
- WAIT FOR 10 us;
+ WAIT FOR 100 us;
csFlag<='1';
read_bus;
- WAIT FOR 10 us;
+ WAIT FOR 100 us;
end process;
END;
diff --git a/2004/n/fpga/src/portserie/rxserie/rxserie.npl b/2004/n/fpga/src/portserie/rxserie/rxserie.npl
index 597ac7c..a400a08 100644
--- a/2004/n/fpga/src/portserie/rxserie/rxserie.npl
+++ b/2004/n/fpga/src/portserie/rxserie/rxserie.npl
@@ -29,10 +29,20 @@ SOURCE sfifo.xco
STIMULUS bch_rxserie.vhd
SOURCE ..\..\modele\nono_const.vhd
SOURCE ..\..\modele\isa_const.vhd
+STIMULUS ..\..\registre\test_reg.vhd
[Normal]
+p_CompxlibOutputDir=xstvhd, spartan2, Design.t_compLibraries, 1079483024, D:\xilinx\vhdl\src
p_CompxlibTargetSimulator=xstvhd, spartan2, Design.t_compLibraries, 1079088462, ModelSim SE
+p_ModelSimListWin=xstvhd, spartan2, VHDL Test Bench.t_MSimulatePostTranslateVhdlModel, 1079738242, False
+p_ModelSimProcWin=xstvhd, spartan2, VHDL Test Bench.t_MSimulatePostTranslateVhdlModel, 1079738242, False
+p_ModelSimSimRunTime_tb=xstvhd, spartan2, VHDL Test Bench.t_MSimulatePostTranslateVhdlModel, 1080007098, 1000us
+p_ModelSimSourceWin=xstvhd, spartan2, VHDL Test Bench.t_MSimulatePostTranslateVhdlModel, 1079738242, False
+p_ModelSimUutInstName_postPar=xstvhd, spartan2, VHDL Test Bench.t_MSimulatePostPlace&RouteVhdlModel, 1079653969, UUT
+p_ModelSimVarsWin=xstvhd, spartan2, VHDL Test Bench.t_MSimulatePostTranslateVhdlModel, 1079738242, False
+_VhdlSimDo_post=xstvhd, spartan2, VHDL Test Bench.t_MSimulatePostTranslateVhdlModel, 1079736489, True
[STATUS-ALL]
-rxserie.ngcFile=WARNINGS,1079226990
-rxserie.ngdFile=WARNINGS,1079300826
+rxserie.ngcFile=WARNINGS,1080007519
+rxserie.ngdFile=WARNINGS,1080007524
+rxserie.postMapVHDLSimModel=WARNINGS,1080007527
[STRATEGY-LIST]
Normal=True
diff --git a/2004/n/fpga/src/portserie/rxserie/rxserie.vhd b/2004/n/fpga/src/portserie/rxserie/rxserie.vhd
index 1ee58ec..e0ec325 100644
--- a/2004/n/fpga/src/portserie/rxserie/rxserie.vhd
+++ b/2004/n/fpga/src/portserie/rxserie/rxserie.vhd
@@ -46,6 +46,7 @@ entity rxserie is
rw : in std_logic; -- read (0) / write (1)
bus_data : inout T_DATA;
clk: in std_logic;
+ clk_ref: in std_logic;
rxin: in std_logic;
irqFIFO: out std_logic;
irqRX: out std_logic;
@@ -110,7 +111,7 @@ end component;
-- signaux
signal rxready:std_logic; -- Receiver data ready to read
-signal rxread:std_logic;
+signal rxread:std_logic:='0';
signal rxparERR:std_logic:='0'; -- Receiver parity error flag
signal rxfrmERR:std_logic:='0'; -- Receiver framing error flag
signal rxovrrERR:std_logic:='0'; -- Receiver overrun error flag
@@ -195,7 +196,7 @@ port map(
-- config
-geneck <= (confreg(4) and clk); -- On/Off et masterck --confreg(4)
+geneck <= (confreg(4) and clk_ref); -- On/Off et clk_ref --confreg(4)
fifopurge<=rst;
-- flags
@@ -208,7 +209,7 @@ flagreg(6) <= rxovrrERR; -- Receiver overrun error flag
-- controle des flux
-fifockout <= (csData and bus_clk and rw and (not rst));
+fifockout <= '1' when (csData='1' and rw='1' and rst='0') else '0';
fifockin <= ((not rxread) and (not fifoFull));
inter_bus <= inter_fifo when (fifockout='1') else (others => 'Z');
@@ -216,9 +217,9 @@ inter_bus <= inter_fifo when (fifockout='1') else (others => 'Z');
bus_data <= inter_bus;
-- irq
-irqFifo <= (fifoLevel(1) and fifoLevel(0)) and confreg(2); --fifo almost full AND Int/En
-irqRx <= (not fifoEmpty) and confreg(3);
-irqErr <= (rxparERR or rxovrrERR or rxfrmERR or fifoFull) and confreg(5);
+irqFifo <= (fifoLevel(1) and fifoLevel(0));-- and confreg(2); --fifo almost full AND Int/En
+irqRx <= (not fifoEmpty);-- and confreg(3);
+irqErr <= (rxparERR or rxovrrERR or rxfrmERR or fifoFull);-- and confreg(5);
-- sortie de donnée du récepteur
process(rxck)
diff --git a/2004/n/fpga/src/portserie/rxserie/sfifo.xco b/2004/n/fpga/src/portserie/rxserie/sfifo.xco
index afcd6a7..61a5042 100644
--- a/2004/n/fpga/src/portserie/rxserie/sfifo.xco
+++ b/2004/n/fpga/src/portserie/rxserie/sfifo.xco
@@ -25,18 +25,17 @@ SET FormalVerification = None
SET OutputProducts = ImpNetlist ASYSymbol VHDLSim VerilogSim
SELECT Synchronous_FIFO Spartan2 Xilinx,_Inc. 4.0
CSET data_width = 8
-CSET read_error_sense = active_high
+CSET read_error_sense = Active_Low
CSET read_error_flag = true
CSET write_acknowledge_flag = true
CSET write_error_flag = true
CSET data_count = true
CSET memory_type = Distributed_Memory
-CSET read_acknowledge_sense = active_high
+CSET read_acknowledge_sense = Active_Low
CSET component_name = sfifo
CSET fifo_depth = 16
CSET read_acknowledge_flag = true
CSET data_count_width = 2
-CSET write_error_sense = active_high
-CSET write_acknowledge_sense = active_high
+CSET write_error_sense = Active_Low
+CSET write_acknowledge_sense = Active_Low
GENERATE
-
diff --git a/2004/n/fpga/src/portserie/uart/txmit.vhd b/2004/n/fpga/src/portserie/uart/txmit.vhd
index 0088729..76bfbf8 100644
--- a/2004/n/fpga/src/portserie/uart/txmit.vhd
+++ b/2004/n/fpga/src/portserie/uart/txmit.vhd
@@ -7,10 +7,10 @@ entity TXMIT is
MCLKX16 : in std_logic;
WRITE : in std_logic;
RESET : in std_logic;
- DATA : in std_logic_vector(7 downto 0);
+ DATA : in std_logic_vector(7 downto 0);
- TX : out std_logic;
- TXRDY : out std_logic
+ TX : out std_logic;
+ TXRDY : out std_logic
);
end TXMIT;
@@ -45,10 +45,12 @@ begin
TXDONE <= not (TAG2 or TAG1 or TSR(7) or TSR(6) or TSR(5) or TSR(4) or TSR(3)
or TSR(2) or TSR(1) or TSR(0));
+
+-- *** AJOUT ***
+ -- Ready for new date to be written, when no data is in transmit hold register.
+-- (ajout :) et quand la transmission est finie !
- -- Ready for new date to be written, when no data is in transmit hold register.
-
- TXRDY <= not TXDATARDY;
+ TXRDY <= TXDONE and not TXDATARDY;
-- Latch data[7:0] into the transmit hold register at posedge of write.