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Diffstat (limited to '2004/n/fpga/src/portserie/txserie.vhd')
-rw-r--r--2004/n/fpga/src/portserie/txserie.vhd15
1 files changed, 10 insertions, 5 deletions
diff --git a/2004/n/fpga/src/portserie/txserie.vhd b/2004/n/fpga/src/portserie/txserie.vhd
index 11e0946..5995f9c 100644
--- a/2004/n/fpga/src/portserie/txserie.vhd
+++ b/2004/n/fpga/src/portserie/txserie.vhd
@@ -97,8 +97,8 @@ end component;
component clockgene
port(
- ck_in: in std_logic;
- ck_out: in std_logic;
+ ckin: in std_logic;
+ ckout: out std_logic;
param: in std_logic_vector(1 downto 0)
);
end component;
@@ -128,6 +128,7 @@ signal busck: std_logic;
--signal rst: std_logic;
signal confreg: unsigned(7 downto 0);
signal flagreg: unsigned(7 downto 0);
+signal interflag: std_logic_vector(5 downto 0);
signal datareg: unsigned(7 downto 0);
signal inter_data: unsigned(7 downto 0);
signal txempty: std_logic;
@@ -143,9 +144,11 @@ FIFO1: fifo
ck=>masterck,
ck_in=>fifockin,
ck_out=>fifockout,
- flags=>flagreg(5 downto 0),
+ flags=>interflag(5 downto 0),
purge=>confreg(3)
);
+
+flagreg(5 downto 0)<=conv_unsigned(CONV_INTEGER(interflag),8);
fifockin<=csFifo and not rw and busck;
fifockout<=txempty; -- ŕ vérifier !!! Cette ligne est valable pour
@@ -161,8 +164,8 @@ TX1 : transmitter
CLOCK1 : clockgene
port map(
- ck_in=>geneck,
- ck_out=>txck,
+ ckin=>geneck,
+ ckout=>txck,
param=>"11" --confreg(1 downto 0)
);
@@ -218,3 +221,5 @@ end rtl;
+
+