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-rw-r--r--2004/n/fpga/src/modele/modele.vhd18
1 files changed, 10 insertions, 8 deletions
diff --git a/2004/n/fpga/src/modele/modele.vhd b/2004/n/fpga/src/modele/modele.vhd
index 701ccbc..366759d 100644
--- a/2004/n/fpga/src/modele/modele.vhd
+++ b/2004/n/fpga/src/modele/modele.vhd
@@ -5,8 +5,10 @@
library ieee;
use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
-use work.nono_const.all
+use work.nono_const.all;
entity modele is
generic (
@@ -23,8 +25,8 @@ entity modele is
-- XXX : savoir si read = 0 ou 1 !!
rw : in std_logic; -- read (0) / write (1)
- bus_data : inout std_logic_vector ((NB_BIT_DATA - 1) downto 0);
- bus_address : in std_logic_vector ((NB_BIT_ADDRESS - 1) downto 0)
+ bus_data : inout unsigned ((NB_BIT_DATA - 1) downto 0);
+ bus_address : in unsigned ((NB_BIT_ADDRESS - 1) downto 0)
);
end entity;
@@ -34,14 +36,14 @@ begin
begin
if (rst = '1') then
bus_data <= x"00";
- elsif (ck'event and ck = '1') then
+ elsif (clk'event and clk = '1') then
if (bus_address = A_REG1) then
- bus_data <= "01";
+ bus_data <= x"01";
else
if (bus_address = A_REG2) then
- bus_data <= "02";
- elsif (bus_address = A_REG2) then
- bus_data <= "03";
+ bus_data <= x"02";
+ elsif (bus_address = A_REG3) then
+ bus_data <= x"03";
end if;
end if;
end if;