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--- reg_rw.vhd
--- Eurobot 2004 : APB Team
--- Auteur : Pierre-André Galmes
--- Registre dont la valeur est accessible en lecture.
-
--- Principe :
--- Si (write et enable) alors sauvegarde entrée et copie entrée sur sortie.
--- Si (read et enable) alors copie dernière valeur sauvegardée sur entrée.
--- Si (pas enable) alors copie dernière valeur sauvegardée sur sortie.
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_arith.all;
-use ieee.std_logic_unsigned.all;
-
-use work.isa_const.all;
-use work.nono_const.all;
-
-
-entity reg_rw is
- port (
- clk : in std_logic;
- rst : in std_logic;
- rw : in std_logic; -- read (ISA_READ) / write (ISA_WRITE)
- enable : in std_logic;
- data : inout T_DATA;
- data_out : out T_DATA -- data courant
- );
-end entity;
-
-architecture RTL of reg_rw is
- -- signal interne
- signal REG : T_DATA;
-begin
- -- partie séquentielle.
- process (rst, clk)
- begin
- -- reset
- if (rst = '1') then
- REG <= (others => '0');
- -- écriture des données.
- elsif (clk'event and clk = '1') then
- if (enable = '1' and rw = ISA_WRITE) then
- REG <= data;
- end if;
- end if;
- end process;
-
- -- partie combinatoire.
- data <= REG when (enable = '1' and rw = ISA_READ) else (others => 'Z');
- data_out <= REG;
-
-end RTL;