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+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+-- Uncomment the following lines to use the declarations that are
+-- provided for instantiating Xilinx primitive components.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity fpga is
+port(
+-- le contrôle général
+ rst : IN std_logic;
+ clk_speed : IN std_logic;
+ clk_ref : IN std_logic;
+
+-- le contrôle de bus
+ AEN : in std_logic;
+ IOR : in std_logic;
+ IOW : in std_logic;
+ bus_adr : in std_logic_vector(23 downto 0);
+ bus_data : INOUT std_logic_vector(7 downto 0);
+ irq : OUT std_logic;
+
+-- les entrées-sorties
+ rxin1:in std_logic
+);
+end fpga;
+
+architecture rtl of fpga is
+
+-- Déclaration des composants
+ COMPONENT rxserie
+ PORT(
+ rst : IN std_logic;
+ bus_clk : IN std_logic;
+ rw : IN std_logic;
+ clk : IN std_logic;
+ clk_ref : IN std_logic;
+ rxin : IN std_logic;
+ csData : IN std_logic;
+ csConfig : IN std_logic;
+ csFlag : IN std_logic;
+ bus_data : INOUT std_logic_vector(7 downto 0);
+ irqFIFO : OUT std_logic;
+ irqRX : OUT std_logic;
+ irqERR : OUT std_logic
+ );
+ END COMPONENT;
+
+ COMPONENT decodisa
+ PORT(
+ adr_bus : IN std_logic_vector(23 downto 0);
+ AEN : IN std_logic;
+ IOR : IN std_logic;
+ IOW : IN std_logic;
+ cs : OUT std_logic_vector(255 downto 0);
+ rw : OUT std_logic;
+ clk : OUT std_logic
+ );
+ END COMPONENT;
+
+
+signal cs : std_logic_vector(255 downto 0);
+signal rw:std_logic;
+signal bus_clk:std_logic;
+
+begin
+-- Instanciation des composants
+
+-- décodeur ISA
+ Inst_decodisa: decodisa PORT MAP(
+ adr_bus => bus_adr,
+ AEN => AEN,
+ IOR => IOR,
+ IOW => IOW,
+ cs => cs,
+ rw => rw,
+ clk => bus_clk
+ );
+
+
+-- RX1
+-- adresse 1
+ Inst_rxserie1: rxserie PORT MAP(
+ rst => rst,
+ bus_clk => bus_clk,
+ rw => rw,
+ bus_data => bus_data,
+ clk => clk_speed,
+ clk_ref => clk_ref,
+ rxin => rxin1,
+ irqFIFO => open,
+ irqRX => open,
+ irqERR => open,
+ csData => cs(1),
+ csConfig => cs(2),
+ csFlag => cs(3)
+ );
+
+
+
+end rtl;